H1A424M167 Просмотр технического описания (PDF) - Hynix Semiconductor
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H1A424M167 Datasheet PDF : 47 Pages
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Hyundai Electronics Industries Co., Ltd.
H1A424M167
31
AD[7]
B Address/Data Bus for MCU interface
32
ALE
I Address Latch Enable
33
IODONE
O CIS/ISP Read/Write Done
34
UV[7]
O Video Data Output for CrCb
35
UV[6]
O Video Data Output for CrCb
36
UV[5]
O Video Data Output for CrCb
37
UV[4]
O Video Data Output for CrCb
38
VDD
P Power Pin, 3.3V
39
RESETB
I ISP Reset, Active Low
40
VSS
G Ground Pin
41
UV[3]
O Video Data Output for CrCb
42
UV[2]
O Video Data Output for CrCb
43
UV[1]
O Video Data Output for CrCb
44
UV[0]
O Video Data Output for CrCb
45
VDD
P Power Pin, 3.3V
46
VCLK
O Pixel Clock for Video Output
47
VSS
G Ground Pin
48
Y[7]
O Video Data Output for Y
49
Y[6]
O Video Data Output for Y
50
Y[5]
O Video Data Output for Y
51
Y[4]
O Video Data Output for Y
52
VDD
P Power Pin, 3.3V
53
VSS
G Ground Pin
54
Y[3]
O Video Data Output for Y
55
Y[2]
O Video Data Output for Y
56
Y[1]
O Video Data Output for Y
57
Y[0]
O Video Data Output for Y
58
HSISP
O Horizontal SYNC Signal for Video Data Output
59
VSISP
O Vertical SYNC Signal for Video Data Output
60
VDD
P Power Pin, 3.3V
61
SCLK/IOR
I Serial Bus Clock for programming ISP, Can be
used as IOR when MCU interface configuration
62
VSS
G Ground Pin
63
SDATA/IOW B Serial Bus Data for programming ISP, Can be
used as IOW when MCU interface configuration
1999 October 11
Page 8
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