HSP48901JC-20 Просмотр технического описания (PDF) - Intersil
Номер в каталоге
Компоненты Описание
производитель
HSP48901JC-20 Datasheet PDF : 9 Pages
| |||
HSP48901
Control Signals
HOLD
The HOLD control input provides the ability to disable
internal clock and stop all operations temporarily. HOLD is
sampled on the rising edge of CLK and takes effect during
the following clock cycle (refer to Figure 2). This signal can
be used to momentarily ignore data at the input of the
convolver while maintaining its current output data and
operational state.
CLK
HOLD
INTERNAL
CLOCK
FIGURE 2. HOLD OPERATION
FRAME
The FRAME input initializes all internal flip flops and
registers except for the coefficient and Initialization
Registers. It is used as a reset between video frames and
eliminates the need to reinitialize the entire HSP48901 or
reload the coefficients. The registers and flip flops will
remain in a reset state as long as FRAME is active. FRAME
is an asynchronous input and may occur at any time.
However, it must be deasserted at least tFS ns prior to the
rising clock edge that is to begin operation for the next frame
in order to ensure the new pixel data is properly loaded.
Operation
A single HSP48901 can be used to perform 3 x 3 convolution
on 8-bit image data. A Block Diagram of this configuration is
shown in Figure 3. The inputs of an external data buffer (such
as the HSP9501) are connected to the input data in parallel
with the DlN1(0-7) lines; the outputs of the data buffer are
connected to the DIN2(0-7) bus. A second external data buffer
is connected between the outputs of the first buffer and the
DIN3(0-7) inputs. To perform the convolution operation, a
group of nine image pixels is multiplied by the 3 x 3 array of
filter coefficients and their products are summed and sent to
the output. For the example in Figure 3, the pixel value in the
output image at location m, n is given by:
DOUT(m,n) = A x Pm-1, n-1 + B x Pm-1,n +C x Pm-1, n+1
+ D x Pm, n-1 + E x Pm, n + F x Pm, n+1
+ G x Pm+1,n-1 + H x Pm+1,n +I xPm+1, n+1
This process is continually repeated until the last pixel of the
last row of the image has been input. It can then start again
with the first row of the next frame. The FRAME pin is used to
clear the Internal Multiplier Registers and DOUT0-19
Registers between frames. The row length of the image to be
convolved is limited only by the maximum length of the
external data buffers.
The setup is straightforward. The user must first setup the
HSP48901 by loading a new value into the Initialization
Register. The coefficients can now be loaded one at a time
from A to I via the CIN0-7 coefficient bus, and the A0-2 and
LD control lines.
IMAGE 8
DATA
DATA
BUFFER
DIN 1 (0 -7)
DOUT 0 -19
DIN 2 (0 -7)
20 FILTERED
IMAGE
DATA
DATA
BUFFER
HSP48901
DIN 3 (0 -7)
INITIALIZATION
DATA
ABC
DE F
FH I
PM -1, N -1
PM, N -1
PM+1, N -1
PM -1, N
PM, N
PM+1, N
PM -1, N +1
PM, N +1
PM+1, N +1
FILTER KERNEL
IMAGE DATA
FIGURE 3. 3 x 3 KERNEL ON AN 8-BIT IMAGE
Multiple filter kernels can also be used on the same image
data using the dual Coefficient Registers CREG0 and
CREG1. This type of filtering is used when the characteristics
of the input pixel data change over the image in such a way
that no one filter produces satisfactory results for the entire
image. In order to filter such an image, the characteristics of
the filter itself must change while the image is being
processed. The HSP48901 can perform this function with the
use of an external processor. The processor is used to
calculate the required new filter coefficients, loads them into
the Coefficient Register not in use, and selects the newly
loaded Coefficient Register at the proper time. The first
Coefficient Register can then be loaded with new coefficients
in preparation for the next change. This can be carried out
with no interruption in processing, provided that the new
register is selected synchronous to the convolver CLK signal.
The HSP48901 can also operate as a one dimensional 9-tap
FIR filter by programming the Initialization Register to 1-D
mode (i.e., INT bit-1 = 0). This configuration will provide for
nine sequential input values to be multiplied by the coefficient
values in the selected Coefficient Register and provide the
proper filtered output. The input bus to be used when
operating in this mode is the DIN1(0-7) inputs.
The equation for the output in the 1-D 9-tap FIR case
becomes:
D0UTn = A x Dn-8 + B x Dn-7 + C x Dn-6 + D x Dn-5
+ E x Dn-4 + F x Dn-3 + G x Dn-2 + H x Dn-1
+ l x Dn
Frame Rate
The total time to process an image is given by the formula:
T = R x C/F, where:
T = Time to process a frame
R = Number of rows in the image
C = Number of pixels in a row
F = Clock rate of the HSP48901
6
Share Link: 