AZ100LVEL16VTMA Просмотр технического описания (PDF) - Arizona Microtek, Inc
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AZ100LVEL16VTMA Datasheet PDF : 13 Pages
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AZ100LVEL16VT
LOGIC DIAGRAMS AND PINOUTS FOR 2x2mm PACKAGE
Q
D
470Ω
VBB
EN
4mA
VEE
QHG
QHG
CMOS / TTL
THRESHOLD
MLP 8, 2x2mm
AZ100LVEL16VTNC
EN operation follows CMOS/TTL
functionality. See Timing Diagram above.
MLP 8, 2x2mm
D 1 AZ100LVEL16VTNC 8 Q
VBB 2
7 VCC
EN 3
VEE 4
TOP VIEW
6 QHG
5 QHG
Bottom Center Pad may be left open
or tied to VEE. Pin 4 is the VEE return.
Q
D
D
470
470
VBB
EN
4mA
VEE
QHG
QHG
CMOS / TTL
THRESHOLD
MLP 8, 2x2mm
AZ100LVEL16VTND
EN operation follows CMOS/TTL
functionality. See Timing Diagram above.
MLP 8, 2x2mm
D1
AZ100LVEL16VTND 8 Q
D2
7 VCC
VEE
VBB 3
6 QHG
EN 4
TOP VIEW
5 QHG
Bottom Center Pad is the VEE return.
April 2007 * REV - 9
www.azmicrotek.com
9
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