AZ100LVEL16VTNC Просмотр технического описания (PDF) - Arizona Microtek, Inc
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AZ100LVEL16VTNC Datasheet PDF : 13 Pages
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AZ100LVEL16VT
LOGIC DIAGRAMS AND PINOUTS FOR 2x2mm PACKAGE
Q
D
D
470 Ω
VBB
470 Ω
4mA
VEE
QHG
QHG
EN
MLP 8, 2x2mm
AZ100LVEL16VTNA
4mA
¯EQ¯N¯ operation follows PECL functionVaEElity.
SDee Ti4m70iΩng Diagram above.
QHG
QHG
VBB
EN
MLP 8, 2x2mm
AZ100LVEL16VTNB
¯E¯N¯ operation follows PECL functionality.
See Timing Diagram above.
MLP 8, 2x2mm
D1
AZ100LVEL16VTNA 8 Q
D2
VBB 3
7 VCC
VEE
6 QHG
EN 4
TOP VIEW
5 QHG
MLP 8, 2x2mm
BottDom1CentAeZr10P0aLdVEisL1t6hVeTVNBEE8retQurn.
VBB 2
7 VCC
EN 3
VEE 4
TOP VIEW
6 QHG
5 QHG
Bottom Center Pad may be left open
or tied to VEE. Pin 4 is the VEE return.
April 2007 * REV - 9
www.azmicrotek.com
8
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