ATV750B-15JI(2001) Просмотр технического описания (PDF) - Atmel Corporation

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производитель

ATV750B-15JI
(Rev.:2001)

High-speed UV Erasable Programmable Logic Device

Atmel Corporation 

Power-up Reset

The registers in the ATV750B(L) is designed to reset during power-up. At a point delayed

slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will

depend on the polarity of the output buffer.

This feature is critical for state machine initialization. However, due to the asynchronous

nature of reset and the uncertainty of how VCC actually rises in the system, the following condi-

tions are required:

1. The VCC rise must be monotonic,

2. After reset occurs, all input and feedback setup times must be met before driving the

clock terms or pin high, and

3. The clock pin, or signals from which clock terms are derived, must remain stable during

tPR.

Parameter

tPR

VRST

Description

Power-up Reset Time

Power-up Reset Voltage

Pin Capacitance

f = 1 MHz, T = 25°C(1)

Typ

Max

CIN

COUT

5

8

6

8

Typ

Max

600

1000

3.8

4.5

Units

ns

V

Units

pF

pF

Conditions

VIN = 0V

VOUT = 0V

10 ATV750B(L)

0301I–08/01

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