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ATTINY9 Просмотр технического описания (PDF) - Atmel Corporation

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ATTINY9 Datasheet PDF : 17 Pages
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3. Overview
This device is low-power CMOS 8-bit microcontrollers based on the compact AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the device achieve throughputs
approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus
processing speed.
3.1. Block Diagram
Figure 3-1. Block Diagram
SRAM
Vcc
RESET
GND
Clock generation
8MHz Calib Osc
External clock
128 kHz Internal Osc
Power
management
and clock
control
Power
Supervision
POR & RESET
Watchdog
Timer
Internal
Reference
CPU
D
A
T
A
B
U
S
I/O
PORTS
Interrupt
ADC
AC
TC 0
(16-bit)
FLASH
PB[3:0]
PCINT[3:0]
INT0
ADC[7:0]
Vcc
AIN0
AIN1
ACO
ADCMUX
OC0A/B
T0
ICP0
3.1.1.
Description
The AVR core combines a rich instruction set with 16 general purpose working registers and system
registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture
is compact and code efficient while achieving throughputs up to ten times faster than conventional CISC
microcontrollers.
This device provides the following features: 512/1024 byte of In-System Programmable Flash, 32 bytes of
SRAM, four general purpose I/O lines, 16 general purpose working registers, a 16-bit timer/counter with
two PWM channels, internal and external interrupts, a programmable watchdog timer with internal
oscillator, an internal calibrated oscillator, and four software selectable power saving modes. ATtiny5/10
are also equipped with a four-channel and 8-bit Analog to Digital Converter (ADC).
Idle mode stops the CPU while allowing the SRAM, timer/counter, ADC (ATtiny5/10, only), analog
comparator, and interrupt system to continue functioning. ADC Noise Reduction mode minimizes
switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC. In
Power-down mode registers keep their contents and all chip functions are disabled until the next interrupt
Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATiny10 [DATASHEET]
9
Atmel-8127H-ATiny4/ ATiny5 /ATiny9/ ATiny10_Datasheet_Summary-11/2016

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