ATTINY88 Просмотр технического описания (PDF) - Atmel Corporation
Номер в каталоге
Компоненты Описание
производитель
ATTINY88 Datasheet PDF : 298 Pages
| |||
ATtiny48/88
1.1 Pin Descriptions
1.1.1 VCC
Digital supply voltage.
1.1.2 GND
Ground.
1.1.3
Port A (PA3:0) (in 32-lead TQFP and 32-pad QFN/MLF packages, only)
Port A is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) in 32-
lead TQFP and 32-pad QFN/MLF package. The PA[3:0] output buffers have symmetrical drive
characteristics with both sink and source capability. As inputs, Port A pins that are externally
pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated
when a reset condition becomes active, even if the clock is not running.
1.1.4
Port B (PB7:0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both sink and source capability.
As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are
activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock
is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the internal clock
operating circuit.
The various special features of Port B are elaborated in “Alternate Functions of Port B” on page
67 and “System Clock and Clock Options” on page 25.
1.1.5
Port C (PC7, PC5:0)
Port C is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
PC7 and PC[5:0] output buffers have symmetrical drive characteristics with both sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
1.1.6
PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char-
acteristics of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a reset input. A low level on this pin for
longer than the minimum pulse width will generate a reset, even if the clock is not running. The
minimum pulse length is given in Table 21-3 on page 207. Shorter pulses are not guaranteed to
generate a reset.
The various special features of Port C are elaborated in “Alternate Functions of Port C” on page
70.
1.1.7
Port D (PD7:0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
PD[7:4] output buffers have symmetrical drive characteristics with both sink and source capabil-
ities, while the PD[3:0] output buffers have high sink capabilities. As inputs, Port D pins that are
3
8008F–AVR–06/10
Share Link: 