ATMEGA64A-MN(2013) Просмотр технического описания (PDF) - Atmel Corporation

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ATMEGA64A-MN
(Rev.:2013)

8-bit Atmel Microcontroller with 64KB In-System Programmable Flash

Atmel Corporation 

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control

is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the inter-

rupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an

interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set

and cleared in software with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the oper-

ated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be

copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic.

See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See

the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Descrip-

tion” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set

Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for

detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for

detailed information.

7.3.2

General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required perfor-

mance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input.

• Two 8-bit output operands and one 8-bit result input.

• Two 8-bit output operands and one 16-bit result input.

• One 16-bit output operand and one 16-bit result input.

Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU.

ATmega64A [DATASHEET]

10

8160D–AVR–02/2013

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