ATF1516AS Просмотр технического описания (PDF) - Atmel Corporation

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ATF1516AS

High Performance EE-Based CPLD

Atmel Corporation 

ATF1516AS/L

Programmable Pin-Keeper Option

for Inputs and I/Os

The ATF1516AS offers the option of programming all input

and I/O pins so that “pin keeper” circuits can be utilized.

When any pin is driven high or low and then subsequently

left floating, it will stay at that previous high or low level.

This circuitry prevents unused input and I/O lines from

floating to intermediate voltage levels, which cause unnec-

essary power consumption and system noise. The keeper

circuits eliminate the need for external pull-up resistors and

eliminate their DC power consumption.

Input Diagram

I/O Diagram

macrocells to be configured for maximum power savings.

This feature may be selected as a design option.

All ATF1516ASs also have an optional power down mode.

In this mode, current drops to below 10 mA. When the

power down option is selected, either PD1 or PD2 pins (or

both) can be used to power down the part. The power down

option is selected in the design source file. When enabled,

the device goes into power down when either PD1 or PD2

is high. In the power down mode, all internal logic signals

are latched and held, as are any enabled outputs.

All pin transitions are ignored until the PD pin is brought

low. When the power down feature is enabled, the PD1 or

PD2 pin cannot be used as a logic input or output. How-

ever, the pin’s macrocell may still be used to generate bur-

ied foldback and cascade logic signals.

All Power-Down AC Characteristic parameters are com-

puted from external input or I/O pins, with Reduced Power

Bit turned on. For macrocells in reduced-power mode

(Reduced power bit turned on), the reduced power adder,

tRPA, must be added to the AC parameters, which include

the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP.

Each output also has individual slew rate control. This may

be used to reduce system noise by slowing down outputs

that do not need to operate at maximum speed. Outputs

default to slow switching, and may be specified as fast

switching in the design file.

Design Software Support

ATF1516AS designs are supported by several third party

tools. Automated fitters allow logic synthesis using a variety

of high level description languages and formats.

Speed/Power Management

The ATF1516AS has several built-in speed and power

management features. The ATF1516AS contains circuitry

that automatically puts the device into a low power stand-

by mode when no logic transitions are occurring. This not

only reduces power consumption during inactive periods,

but also provides a proportional power savings for most

applications running at system speeds below 50 MHz.

To further reduce power, each ATF1516AS macrocell has

a Reduced Power bit feature. This feature allows individual

Power Up Reset

The ATF1516AS has a power-up reset option at two differ-

ent voltage trip levels when the device is being powered

down. Within the fitter, or during a conversion, if the

“power-reset” option is turned “on” (which is the default

option), the trip levels during power up or power down is at

2.8V. The user can change this default option from “on” to

“off” (within the fitter or specify it as a switch during conver-

sion). When this is done, the voltage trip level during

power-down changes from 2.8V to 0.7V. This is to ensure a

robust operating environment.

The registers in the ATF1516AS are designed to reset dur-

ing power up. At a point delayed slightly from VCC crossing

VRST, all registers will be reset to the low state. The output

state will depend on the polarity of the buffer.

This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the

uncertainty of how VCC actually rises in the system, the fol-

lowing conditions are required:

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