ATF1508ASVL(2000) Просмотр технического описания (PDF) - Atmel Corporation

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ATF1508ASVL
(Rev.:2000)

High performance EE PLD

Atmel Corporation 

ATF1508ASV(L)

Design Software Support

ATF1508ASV(L) designs are supported by several third-

party tools. Automated fitters allow logic synthesis using a

variety of high-level description languages and formats.

Power-up Reset

The ATF1508ASV is designed with a power-up reset, a

feature critical for state machine initialization. At a point

delayed slightly from VCC crossing VRST, all registers will be

initialized, and the state of each output will depend on the

polarity of its buffer. However, due to the asynchronous

nature of reset and uncertainty of how VCC actually rises in

the system, the following conditions are required:

1. The VCC rise must be monotonic,

2. After reset occurs, all input and feedback setup

times must be met before driving the clock pin

high, and,

3. The clock must remain stable during TD.

The ATF1508ASV has two options for the hysteresis about

the reset level, VRST, Small and Large. To ensure a robust

operating environment in applications where the device is

operated near 3.0V, Atmel recommends that during the fit-

ting process users configure the device with the Power-up

Reset hysteresis set to Large. For conversions, Atmel

POF2JED users should include the flag “-power_reset” on

the command line after “filename.POF”. To allow the regis-

ters to be properly reinitialized with the Large hysteresis

option selected, the following condition is added:

4. If VCC falls below 2.0V, it must shut off com-

pletely before the device is turned on again.

When the Large hysteresis option is active, ICC is reduced

by several hundred microamps as well.

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying

of the ATF1508ASV(L) fuse patterns. Once programmed,

fuse verify is inhibited. However, User Signature and

device ID remains accessible.

Programming

ATF1508ASV(L) devices are in-system programmable

(ISP) devices utilizing the 4-pin JTAG protocol. This capa-

bility eliminates package handling normally required for

programming and facilitates rapid design iterations and

field changes.

Atmel provides ISP hardware and software to allow pro-

gramming of the ATF1508ASV(L) via the PC. ISP is per-

formed by using either a download cable, a comparable

board tester or a simple microprocessor interface.

To allow ISP programming support by the Automated Test

Equipment (ATE) vendors, Serial Vector Format (SVF) files

can be created by the Atmel ISP software. Conversion to

other ATE tester format beside SVF is also possible

ATF1508ASV(L) devices can also be programmed using

standard third-party programmers. With third-party pro-

grammer, the JTAG ISP port can be disabled thereby

allowing four additional I/O pins to be used for logic.

Contact your local Atmel representatives or Atmel PLD

applications for details.

ISP Programming Protection

The ATF1508ASV(L) has a special feature that locks the

device and prevents the inputs and I/O from driving if the

programming process is interrupted for any reason. The

inputs and I/O default to high-Z state during such a condi-

tion. In addition the pin-keeper option preserves the former

state during device programming.

All ATF1508ASV(L) devices are initially shipped in the

erased state thereby making them ready to use for ISP.

Note:

For more information refer to the “Designing for In-Sys-

tem Programmability with Atmel CPLDs” application

note.

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