ATF1504BE Просмотр технического описания (PDF) - Atmel Corporation

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ATF1504BE

High-performance CPLD

Atmel Corporation 

Figure 1-3. Block Diagram

8 or 16

8 or 16

ATF1504BE

I/O (MC64)/GCLK3

3637B–PLD–1/08

Each of the 64 macrocells generates a buried feedback signal that goes to the global bus (see

Figure 1-3). Each input and I/O pin also feeds into the global bus. The switch matrix in each logic

block then selects 40 individual signals from the global bus. Each macrocell also generates a

foldback logic term that goes to a regional bus. Cascade logic between macrocells in the

ATF1504BE allows fast, efficient generation of complex logic functions. The ATF1504BE con-

tains eight such logic chains, each capable of creating sum term logic with a fan-in of up to 40

product terms.

The ATF1504BE macrocell, shown in Figure 1-4, is highly flexible and capable of supporting

complex logic functions operating at high speed. The macrocell consists of five sections: product

terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select

and enable, and logic array inputs.

A security fuse, when programmed, protects the contents of the ATF1504BE. Two bytes

(16 bits) of User Electronic Signature are accessible to the user for purposes such as storing

project name, part number, revision or date. The User Electronic Signature is accessible regard-

less of the state of the security fuse.

The ATF1504BE device supports In-System Programming (ISP) via the industry-standard 4-pin

JTAG interface (IEEE 1532 standard), and is fully compliant with IEEE 1149.1 for Boundary

Scan Test. ISP allows the device to be programmed without removing it from the printed circuit

board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to

be made in the field via software.

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