ATF1502ASV Просмотр технического описания (PDF) - Atmel Corporation

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ATF1502ASV

High performance EEPROM CPLD

Atmel Corporation 

floating to intermediate voltage levels, which causes unnecessary power consumption and sys-

tem noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate

their DC power consumption.

Figure 2-1. Input Diagram

VCC

INPUT

100K

ESD

PROTECTION

CIRCUIT

PROGRAMMABLE

OPTION

Figure 2-2. I/O Diagram

VCC

OE

DATA

I/O

VCC

100K

PROGRAMMABLE

OPTION

3. Speed/Power Management

The ATF1502ASV has several built-in speed and power management features.

To further reduce power, each ATF1502ASV macrocell has a reduced-power bit feature. To

reduce power consumption this feature may be actived (by changing the default value of OFF to

ON) for any or all macrocells.

The ATF1502ASV also has an optional power-down mode. In this mode, current drops to below

15 mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used

to power down the part. The power-down option is selected in the design source file. When

enabled, the device goes into power-down when either PD1 or PD2 is high. In the power-down

mode, all internal logic signals are latched and held, as are any enabled outputs.

6 ATF1502ASV

1615J–PLD–01/06

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