ATF1502ASV Просмотр технического описания (PDF) - Atmel Corporation

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ATF1502ASV

High performance EEPROM CPLD

Atmel Corporation 

the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design

modifications to be made in the field via software.

Figure 1-4. ATF1502ASV Macrocell

1.1 Product Terms and Select Mux

Each ATF1502ASV macrocell has five product terms. Each product term receives as its inputs

all signals from both the global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the five product terms as needed to the

macrocell logic gates and control signals. The PTMUX programming is determined by the design

compiler, which selects the optimum macrocell configuration.

1.2 OR/XOR/CASCADE Logic

The ATF1502ASV’s logic structure is designed to efficiently support all types of logic. Within a

single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR

sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to

as many as 40 product terms with little additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions.

One input to the XOR comes from the OR sum term. The other XOR input can be a product term

or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selec-

tion. For registered functions, the fixed levels allow DeMorgan minimization of product terms.

The XOR gate is also used to emulate T- and JK-type flip-flops.

4 ATF1502ASV

1615J–PLD–01/06

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