ATF1502ASV(2004) Просмотр технического описания (PDF) - Atmel Corporation

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производитель

ATF1502ASV
(Rev.:2004)

High performance EEPROM CPLD

Atmel Corporation 

Boundary-scan Description Language (BSDL). ISP allows the device to be programmed

without removing it from the printed circuit board. In addition to simplifying the manufac-

turing flow, ISP also allows design modifications to be made in the field via software.

Figure 1. ATF1502ASV Macrocell

Product Terms and

Select Mux

OR/XOR/

CASCADE Logic

Each ATF1502ASV macrocell has five product terms. Each product term receives as its

inputs all signals from both the global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the five product terms as

needed to the macrocell logic gates and control signals. The PTMUX programming is

determined by the design compiler, which selects the optimum macrocell configuration.

The ATF1502ASV’s logic structure is designed to efficiently support all types of logic.

Within a single macrocell, all the product terms can be routed to the OR gate, creating a

5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells,

this can be expanded to as many as 40 product terms with little additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic

functions. One input to the XOR comes from the OR sum term. The other XOR input can

be a product term or a fixed high or low level. For combinatorial outputs, the fixed level

input allows polarity selection. For registered functions, the fixed levels allow DeMorgan

minimization of product terms. The XOR gate is also used to emulate T- and JK-type

flip-flops.

4 ATF1502ASV

1615H–PLD–2/04

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