ATF1502AS Просмотр технического описания (PDF) - Atmel Corporation

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ATF1502AS

High Performance E2PROM CPLD

Atmel Corporation 

ATF1502AS(L)

JTAG

Boundary-scan

Cell (BSC)

Testing

The ATF1502AS contains up to 32 I/O pins and four input pins, depending on the device type

and package type selected. Each input pin and I/O pin has its own boundary-scan cell (BSC)

in order to support boundary-scan testing as described in detail by IEEE Standard 1149.1. A

typical BSC consists of three capture registers or scan registers and up to two update regis-

ters. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The

BSCs in the device are chained together through the capture registers. Input to the capture

register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture

registers are used to capture active device data signals, to shift data in and out of the device

and to load data into the update registers. Control signals are generated internally by the

JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells is

shown below.

BSC

Configuration

for Input and I/O

Pins (Except

JTAG TAP Pins)

BSC

Configuration

for Macrocell

Note: 1. The ATF1502AS has a pull-up option on TMS and TDI pins. This feature is selected as a

design option.

TDO

QD

0

1

CLOCK

TDI

OEJ

0

1

TDO

DQ

0

1

DQ

OUTJ

0

DQ

1

0

1

Pin

DQ

Capture

DR

Update

DR

TDI

Shift

Clock

Mode

BSC for I/O Pins and Macrocells

9

0995K–PLD–6/05

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