AT90S8515 Просмотр технического описания (PDF) - Atmel Corporation

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AT90S8515

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

Architectural

Overview

AT90S8515

The fast-access register file concept contains 32 x 8-bit general-purpose working regis-

ters with a single clock cycle access time. This means that during one single clock cycle,

one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from

the register file, the operation is executed and the result is stored back in the register file

– in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for

Data Space addressing, enabling efficient address calculations. One of the three

address pointers is also used as the address pointer for the constant table look-up func-

tion. These added function registers are the 16-bit X-, Y-, and Z-register.

The ALU supports arithmetic and logic functions between registers or between a con-

stant and a register. Single register operations are also executed in the ALU. Figure 4

shows the AT90S8515 AVR RISC microcontroller architecture.

In addition to the register operation, the conventional memory addressing modes can be

used on the register file as well. This is enabled by the fact that the register file is

assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be

accessed as though they were ordinary memory locations.

The I/O memory space contains 64 addresses for CPU peripheral functions such as

Control Registers, Timer/Counters, A/D converters and other I/O functions. The I/O

memory can be accessed directly or as the Data Space locations following those of the

register file, $20 - $5F.

The AVR uses a Harvard architecture concept – with separate memories and buses for

program and data. The program memory is executed with a two-stage pipeline. While

one instruction is being executed, the next instruction is pre-fetched from the program

memory. This concept enables instructions to be executed in every clock cycle. The pro-

gram memory is In-System Programmable Flash memory.

With the relative jump and call instructions, the whole 4K address space is directly

accessed. Most AVR instructions have a single 16-bit word format. Every program

memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is

stored on the stack. The stack is effectively allocated in the general data SRAM and

consequently, the stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP in the reset routine (before subroutines

or interrupts are executed). The 16-bit Stack Pointer (SP) is read/write-accessible in the

I/O space.

The 512-byte data SRAM can be easily accessed through the five different addressing

modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

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