AT90S1200 Просмотр технического описания (PDF) - Atmel Corporation
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AT90S1200 Datasheet PDF : 71 Pages
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AT90S1200
EEPROM Read/Write
Access
The EEPROM access registers are accessible in the I/O space.
The write access time is in the range of 2.5 - 4 ms, depending on the VCC voltages. A
self-timing function, however, lets the user software detect when the next byte can be
written. If the user code contains code that writes the EEPROM, some precaution must
be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-
up/down. This causes the device for some period of time to run at a voltage lower than
specified as minimum for the clock frequency used. CPU operation under these condi-
tions is likely cause the program counter to perform unintentional jumps and eventually
execute the EEPROM write code. To secure EEPROM integrity, the user is advised to
use an external under-voltage reset circuit in this case.
In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-
lowed. Refer to “EEPROM Control Register – EECR” on page 25 for details on this.
When the EEPROM is read or written, the CPU is halted for two clock cycles before the
next instruction is executed.
EEPROM Address Register –
EEAR
Bit
7
$1E
–
Read/Write
R
Initial Value
0
6
5
4
3
2
1
0
–
EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEAR
R
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
• Bit 7, 6 – Res: Reserved Bits
These bits are reserved bits in the AT90S1200 and will always read as zero.
• Bits 5..0 – EEAR5..0: EEPROM Address
The EEPROM Address Register (EEAR5..0) specifies the EEPROM address in the 64-
byte EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
63.
EEPROM Data Register –
EEDR
Bit
7
6
5
4
3
2
1
0
$1D
MSB
LSB
EEDR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bits 7..0 – EEDR7..0: EEPROM Data
For the EEPROM write operation, the EEDR register contains the data to be written to
the EEPROM in the address given by the EEAR register. For the EEPROM read opera-
tion, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
EEPROM Control Register –
EECR
Bit
7
6
5
4
3
2
1
0
$1C
–
–
–
–
–
–
EEWE EERE
EECR
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bits 7..2 – Res: Reserved Bits
These bits are reserved bits in the AT90S1200 and will always be read as zero.
25
0838H–AVR–03/02
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