AT89S852-12PC Просмотр технического описания (PDF) - Atmel Corporation

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AT89S852-12PC

8 bit Microcontroller with 8K bytes Flash

Atmel Corporation 

AT89S8252

Serial Peripheral Interface (Continued)

The interconnection between master and slave CPUs with

SPI is shown in the following figure. The SCK pin is the

clock output in the master mode but is the clock input in

the slave mode. Writing to the SPI data register of the

master CPU starts the SPI clock generator, and the data

written shifts out of the MOSI pin and into the MOSI pin of

the slave CPU. After shifting one byte, the SPI clock gen-

erator stops, setting the end of transmission flag (SPIF). If

both the SPI interrupt enable bit (SPIE) and the serial port

interrupt enable bit (ES) are set, an interrupt is requested.

The Slave Select input, SS/P1.4, is set low to select an

individual SPI device as a slave. When SS/P1.4 is set

high, the SPI port is deactivated and the MOSI/P1.6 pin

can be used as an input.

There are four combinations of SCK phase and polarity

with respect to serial data, which are determined by con-

trol bits CPHA and CPOL. The SPI data transfer formats

are shown in Figures 8 and 9.

Figure 7. SPI Master -Slave Interconnection

Figure 8. SPI Transfer Format with CPHA = 0

∗ Not defined but normally MSB of character just received.

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