AT28C64/X Просмотр технического описания (PDF) - Atmel Corporation

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AT28C64/X

64K (8K x 8) CMOS E2PROM

Atmel Corporation 

AT28C64/X

Device Operation

READ: The AT28C64 is accessed like a Static RAM.

When CE and OE are low and WE is high, the data stored

at the memory location determined by the address pins is

asserted on the outputs. The outputs are put in a high im-

pedance state whenever CE or OE is high. This dual line

control gives designers increased flexibility in preventing

bus contention.

BYTE WRITE: Writing data into the AT28C64 is similar to

writing into a Static RAM. A low pulse on the WE or CE

input with OE high and CE or WE low (respectively) initi-

ates a byte write. The address location is latched on the

falling edge of WE (or CE); the new data is latched on the

rising edge. Internally, the device performs a self-clear be-

fore write. Once a byte write has been started, it will auto-

matically time itself to completion. Once a programming

operation has been initiated and for the duration of tWC, a

read operation will effectively be a polling operation.

FAST BYTE WRITE: The AT28C64E offers a byte write

time of 200 µs maximum. This feature allows the entire

device to be rewritten in 1.6 seconds.

READY/BUSY: Pin 1 is an open drain READY/BUSY

output that can be used to detect the end of a write cycle.

RDY/BUSY is actively pulled low during the write cycle

and is released at the completion of the write. The open

drain connection allows for OR-tying of several devices to

the same RDY/BUSY line. Pin 1 is not connected for the

AT28C64X.

DATA POLLING: The AT28C64 provides DATA POLL-

ING to signal the completion of a write cycle. During a

write cycle, an attempted read of the data being written

results in the complement of that data for I/O7 (the other

outputs are indeterminate). When the write cycle is fin-

ished, true data appears on all outputs.

WRITE PROTECTION: Inadvertent writes to the device

are protected against in the following ways. (a) VCC

sense— if VCC is below 3.8V (typical) the write function is

inhibited. (b) VCC power on delay— once VCC h a s

reached 3.8V the device will automatically time out 5 ms

(typical) before allowing a byte write. (c) Write Inhibit—

holding any one of OE low, CE high or WE high inhibits

byte write cycles.

CHIP CLEAR: The contents of the entire memory of the

AT28C64 may be set to the high state by the CHIP CLEAR

operation. By setting CE low and OE to 12 volts, the chip

is cleared when a 10 msec low pulse is applied to WE.

DEVICE IDENTIFICATION: A n e x t ra 32 -byt es of

E2PROM memory are available to the user for device

identification. By raising A9 to 12 ± 0.5V and using ad-

dress locations 1FE0H to 1FFFH the additional bytes may

be written to or read from in the same manner as the regu-

lar memory array.

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