AD7729 Просмотр технического описания (PDF) - Analog Devices

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AD7729

Dual Sigma-Delta ADC with Auxiliary DAC

Analog Devices 

Pin

Number

15

13

Mnemonic

MCLK

RESETB

Power Supply

6

5

7

25

24

AVDD1

AVDD2

AGND

DVDD1

DVDD2

23

DGND

Analog Signal and Reference

1, 2

IRxP, IRxN

3, 4

QRxP, QRxN

26

AUXDAC

28

REFCAP

27

REFOUT

Auxiliary Serial Port (ASPORT)

10

ASCLK

9

ASDI

8

ASDIFS

20

ASDO

21

ASDOFS

22

ASE

Baseband Serial Port (BSPORT)

16

BSCLK

12

BSDI

11

BSDIFS

17

BSDO

18

19

ADCs

14

BSDOFS

BSE

RxON

REV. 0

PIN FUNCTION DESCRIPTIONS

AD7729

Function

Master Clock Input. MCLK is driven from a 13 MHz crystal. The active levels for MCLK are

determined by the value of DVDD2.

Active Low Reset Signal. This input resets the entire AD7729 chip, resetting the control

registers and clearing the digital filters. The logic input levels (VINH and VINL) for RESETB

are determined by the value of DVDD2.

Analog Power Supply Connection for the Rx Section and the Bandgap Reference.

Analog Power Supply Connection for the Auxiliary Section.

Analog Ground Connection.

Digital Power Supply Connection.

Digital Power Supply Connection for the Serial Interface Section. This power supply also sets

the threshold voltages for RxON, RESETB and MCLK.

Digital Ground Connection.

Differential Analog Input for I Receive Channel.

Differential Analog Input for Q Receive Channel.

Analog Output Voltage from the 10-Bit Auxiliary DAC AUXDAC. This DAC is used for

functions such as Automatic Gain Control (AGC). The DAC possesses a register that is

accessible via the ASPORT or BSPORT. The DAC may be individually powered down.

A bypass capacitor to AGND of 0.1 µF is required for the on-chip reference. The capacitor

should be fixed to this pin.

Buffered Reference Output, which has a nominal value of 1.3 V. A bypass capacitor (to

AGND) of 0.1 µF is required on this pin.

Serial Clock used to clock data or control bits to and from the auxiliary serial port (ASPORT).

The frequency of ASCLK is programmable and is equal to the frequency of the master clock

(MCLK) divided by an integer number.

Serial Data Input of ASPORT. Both data and control information are input on this pin.

Input Framing Signal for ASDI Serial Transfers.

Serial Data Output of ASPORT. Both data and control information are output on this pin.

ASDO is in three-state when no information is being transmitted, thereby allowing external

control.

Output Framing Signal for ASDO Serial Transfers.

ASPORT Enable. When ASE is low, the ASPORT is put into three-state thereby allowing

external control of the serial bus.

Output serial clock used to clock data or control bits to and from the baseband serial port

(BSPORT). The frequency of BSCLK is programmable and is equal to the frequency of the

master clock (MCLK) divided by an integer number.

Serial Data Input of BSPORT. Both data and control information are input on this pin.

Input Framing Signal for BSDI Serial Transfers.

Serial Data Output of BSPORT. Both data and control information are output on this pin.

BSDO is in three-state when no information is being transmitted, thereby allowing external

control.

Output Framing Signal for BSDO Serial Transfers.

BSPORT Enable. When BSE is low, the BSPORT is put into three-state thereby allowing

external control of the serial bus.

Receive Section Power-On Digital Input. The receive section is powered up by taking pin

RxON high. The receive section can alternatively be powered up by programming bit RxON

in baseband control register BCRA. When the powering up/down of the receive section is

being controlled by pin RxON, bit RxON should equal zero. Similarly, when the powering up/

down of the receive section is being controlled by bit RxON, pin RxON should be tied low.

The logic input levels (VINH and VINL) for RxON are determined by the value of DVDD2.

–7–

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