AT25DF021 Просмотр технического описания (PDF) - Atmel Corporation

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производитель

AT25DF021

2-Megabit 2.3-volt or 2.7-volt Minimum SPI Serial Flash Memory

Atmel Corporation 

Figure 2-1. 8-SOIC Top View

CS 1

SO 2

WP 3

GND 4

8 VCC

7 HOLD

6 SCK

5 SI

Figure 2-2. 8-UDFN (Top View)

CS 1

SO 2

WP 3

GND 4

8 VCC

7 HOLD

6 SCK

5 SI

3. Block Diagram

Figure 3-1. Block Diagram

CS

SCK

INTERFACE

SI

CONTROL

AND

SO

LOGIC

WP

HOLD

CONTROL AND

PROTECTION LOGIC

Y-DECODER

X-DECODER

I/O BUFFERS

AND LATCHES

SRAM

DATA BUFFER

Y-GATING

FLASH

MEMORY

ARRAY

4. Memory Array

To provide the greatest flexibility, the memory array of the AT25DF021 can be erased in four lev-

els of granularity including a full chip erase. In addition, the array has been divided into physical

sectors of uniform size, of which each sector can be individually protected from program and

erase operations. The size of the physical sectors is optimized for both code and data storage

applications, allowing both code and data segments to reside in their own isolated regions. The

Memory Architecture Diagram illustrates the breakdown of each erase level as well as the

breakdown of each physical sector.

4 AT25DF021

3677D–DFLASH–04/09

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