AT25F512B Просмотр технического описания (PDF) - Atmel Corporation
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AT25F512B Datasheet PDF : 34 Pages
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AT25F512B [Preliminary]
Table 11-1. Status Register Format
Bit(1)
Name
Type(2)
Description
7
BPL
Block Protection Locked
0 BP0 bit unlocked (default).
R/W
1 BP0 bit locked in current state when WP asserted.
6
RES Reserved for future use
R
0 Reserved for future use.
5
EPE Erase/Program Error
0 Erase or program operation was successful.
R
1 Erase or program error detected.
4
WPP Write Protect (WP) Pin Status
0 WP is asserted.
R
1 WP is deasserted.
3
RES Reserved for future use
R
0 Reserved for future use.
2
BP0
Block Protection
0 Entire memory array is unprotected.
R/W
1 Entire memory array is protected.
1
WEL Write Enable Latch Status
0 Device is not write enabled (default).
R
1 Device is write enabled.
0 RDY/BSY Ready/Busy Status
0 Device is ready.
R
1 Device is busy with an internal operation.
Notes: 1. Only bits 7 and 2 of the Status Register can be modified when using the Write Status Register command.
2. R/W = Readable and writable
R = Readable only
11.1.1 BPL Bit
The BPL bit is used to control whether the Block Protection (BP0) bit can be modified or not.
When the BPL bit is in the logical “1” state and the WP pin is asserted, the BP0 bit will be locked
and cannot be modified. The memory array will be locked in the current protected or unprotected
state.
When the BPL bit is in the logical “0” state, the BP0 bit will be unlocked and can be modified.
The BPL bit defaults to the logical “0” state after device power-up.
The BPL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin
is asserted, then the BPL bit may only be changed from a logical “0” (BP0 bit unlocked) to a log-
ical “1” (BP0 bit locked). In order to reset the BPL bit back to a logical “0” using the Write Status
Register command, the WP pin will have to first be deasserted.
The BPL and BP0 bits are the only bits of the Status Register that can be user modified via the
Write Status Register command.
11.1.2 EPE Bit
The EPE bit indicates whether the last erase or program operation completed successfully or
not. If at least one byte during the erase or program operation did not erase or program properly,
then the EPE bit will be set to the logical “1” state. The EPE bit will not be set if an erase or pro-
gram operation aborts for any reason such as an attempt to erase or program the memory when
it is protected or if the WEL bit is not set prior to an erase or program operation. The EPE bit will
be updated after every erase and program operation.
17
3689C–DFLASH–12/08
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