AT25F512B Просмотр технического описания (PDF) - Atmel Corporation
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AT25F512B Datasheet PDF : 34 Pages
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10.2
Read OTP Security Register
The OTP Security Register can be sequentially read in a similar fashion to the Read Array oper-
ation up to the maximum clock frequency specified by fCLK. To read the OTP Security Register,
the CS pin must first be asserted and the opcode of 77h must be clocked into the device. After
the opcode has been clocked in, the three address bytes must be clocked in to specify the start-
ing address location of the first byte to read within the OTP Security Register. Following the
three address bytes, two dummy bytes must be clocked into the device before data can be
output.
After the three address bytes and the dummy bytes have been clocked in, additional clock
cycles will result in OTP Security Register data being output on the SO pin. When the last byte
(00007Fh) of the OTP Security Register has been read, the device will continue reading back at
the beginning of the register (000000h). No delays will be incurred when wrapping around from
the end of the register to the beginning of the register.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-
ance state. The CS pin can be deasserted at any time and does not require that a full byte of
data be read.
Figure 10-2. Read OTP Security Register
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36
OPCODE
ADDRESS BITS A23-A0
DON'T CARE
0 1 1 1 0 1 1 1AAAAAA
MSB
MSB
HIGH-IMPEDANCE
AAAXXXXXX
MSB
XXX
DATA BYTE 1
DDDDDDDDDD
MSB
MSB
11. Status Register Commands
11.1
Read Status Register
The Status Register can be read to determine the device’s ready/busy status, as well as the sta-
tus of many other functions such as Hardware Locking and Block Protection. The Status
Register can be read at any time, including during an internally self-timed program or erase
operation.
To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be
clocked into the device. After the opcode has been clocked in, the device will begin outputting
Status Register data on the SO pin during every subsequent clock cycle. After the last bit (bit 0)
of the Status Register has been clocked out, the sequence will repeat itself starting again with bit
7 as long as the CS pin remains asserted and the clock pin is being pulsed. The data in the Sta-
tus Register is constantly being updated, so each repeating sequence will output new data.
Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin
into a high-impedance state. The CS pin can be deasserted at any time and does not require
that a full byte of data be read.
16 AT25F512B [Preliminary]
3689C–DFLASH–12/08
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