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AT25040A-W1.8-11

SPI Serial EEPROM

Atmel Corporation 

3348J–SEEPR–8/06

AT25010A/020A/040A

the data within any selected segment will therefore be read only. The block write protec-

tion levels and corresponding status register control bits are shown in Table 8.

Bits BP1 and BP0 are nonvolatile cells that have the same properties and functions as

the regular memory cells (e.g., WREN, tWC, RDSR).

Table 8. Block Write Protect Bits

Level

0

1 (1/4)

2 (1/2)

3 (All)

Status Register Bits

BP1

BP0

0

0

0

1

1

0

1

1

Array Addresses Protected

AT25010A

AT25020A

AT25040A

None

None

None

60−7F

C0−FF

180−1FF

40−7F

80−FF

100−1FF

00−7F

00−FF

000−1FF

READ SEQUENCE (READ): Reading the AT25010A/020A/040A via the SO pin

requires the following sequence. After the CS line is pulled low to select a device, the

read op-code (including A8) is transmitted via the SI line followed by the byte address to

be read (A7−A0). Upon completion, any data on the SI line will be ignored. The data

(D7−D0) at the specified address is then shifted out onto the SO line. If only one byte is

to be read, the CS line should be driven high after the data comes out. The read

sequence can be continued since the byte address is automatically incremented and

data will continue to be shifted out. When the highest address is reached, the address

counter will roll over to the lowest address allowing the entire memory to be read in one

continuous read cycle.

WRITE SEQUENCE (WRITE): In order to program the AT25010A/020A/040A, the Write

Protect pin (WP) must be held high and two separate instructions must be executed.

First, the device must be write enabled via the WREN instruction. Then a Write (WRITE)

instruction may be executed. Also, the address of the memory location(s) to be pro-

grammed must be outside the protected address field location selected by the block

write protection level. During an internal write cycle, all commands will be ignored

except the RDSR instruction.

A Write instruction requires the following sequence. After the CS line is pulled low to

select the device, the WRITE op-code (including A8) is transmitted via the SI line fol-

lowed by the byte address (A7−A0) and the data (D7−D0) to be programmed.

Programming will start after the CS pin is brought high. The low-to-high transition of the

CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB)

data bit.

The ready/busy status of the device can be determined by initiating a Read Status Reg-

ister (RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the

write cycle has ended. Only the RDSR instruction is enabled during the write program-

ming cycle.

The AT25010A/020A/040A is capable of an 8-byte page write operation. After each byte

of data is received, the three low-order address bits are internally incremented by one;

the six high-order bits of the address will remain constant. If more than 8 bytes of data

are transmitted, the address counter will roll over and the previously written data will be

overwritten. The AT25010A/020A/040A is automatically returned to the write disable

state at the completion of a write cycle.

NOTE: If the WP pin is brought low or if the device is not write enabled (WREN), the

device will ignore the Write instruction and will return to the standby state, when CS is

brought high. A new CS falling edge is required to reinitiate the serial communication.

9

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