ASCELL3912 Просмотр технического описания (PDF) - austriamicrosystems AG

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ASCELL3912

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell

austriamicrosystems AG 

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell – Preliminary Data Sheet

ASCell3912

Austria Mikro Systeme International AG

1.2 Digital Controller

The principal function of the digital controller is demodulation, bit synchronization and the detec-

tion of the received data protocol, according to the definition of transmitted bits. Furthermore, a

first syntax check and plausibility check of detected data is provided. A data protocol received

completely is put into a receive buffer, where a micro controller (µC) can read it out via a serial

interface.

The receiver can be externally configured with several operation parameters, LNA gain setting,

used frequency band, and timing constant for the watch dog timer. The serial interface also al-

lows to configure the digital controller by the µC.

The receiver writes the state information into a status register. This status information can be

read out from the µC out of the status register of the receiver.

1.2.1 Microprocessor Clock

The microprocessor clock frequency FCLK is generated by dividing the XTAL frequency FXOSC by

4 if XO-SEL is ´H´ and by dividing the XTAL frequency FXOSC by 6 if XO-SEL is ´L´.

Note: XO-SEL and RF-SEL are internal generated signals from the FB[1:0] bits of the setup information.

1.2.2 ASCell3912 Digital Part Timing

In Figure 2 the timing of a complete receive sequence can be seen. Transmission starts at an

arbitrary point in time. First the crystal oscillator is switched on. A minimum time of 5 ms is al-

lowed for the frequency to settle to the final value. Then the receiver executes a wake-up se-

quence consisting of 6 wake-up bursts. The wake-up bursts are unequally spaced to guarantee

interference free detection of an ongoing transmission also in the presence of burst interferers.

During a wake-up burst the receiver scans for an active transmission on the air interface. The

wake-up sequence is optimized to combat GSM and CT2 type interferers.

After an ongoing transmission has been detected the receiver goes to receiving mode, the

WAKE_UP line goes high, and reception of data starts. Depending on the number of interferers

present, reception of all data may take up to 3 data blocks. As soon as all data has been de-

tected successfully, the RE_INT pin issues a positive pulse, to indicate the availability of data,

and the internal data ready flag (DR) in the ASCell3912 state register is set. The RE_INT line

may be used to trigger a interrupt procedure, which is executed at the availability of data. When

data is read out by the micro controller the internal data ready flag (DR) in the RX-status register

is cleared and it is only set, when a complete data sequence has received again. No further

pulse is issued on the RE_INT line, but the micro controller has to poll for new data during an

ongoing reception. If transmission stops, the WAKE_UP line goes low and a pulse is issued on

the RE_INT line to indicate the termination of transmission at CMT.

In Figure 2 also the timing where the microprocessor clock (µC_CLK) is active is shown. The

clock is active with the start of the detection phase of the SC3911. The clock is shut down 16

clock cycles (TCAI) after the falling edge of the second interrupt on the RE_INT pin.

Rev. A, February 2000

Page 5 of 14

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