ASCELL3912 Просмотр технического описания (PDF) - austriamicrosystems AG
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ASCELL3912 Datasheet PDF : 14 Pages
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ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell – Preliminary Data Sheet
ASCell3912
Austria Mikro Systeme International AG
2.5 Digital Pin Characteristics
TAMB = 23 °C, VDD = 3.6 V, unless specified otherwise. GND is the 0 V reference.
Symbol Parameter
Conditions
Min
Typ
Max
µC_CLK (µC clock output)
VOH High level output voltage IOH =-1 mA
VDD-0.5
-
VOL Low level output voltage IOL =1 mA
-
0.3
tr Rise time
CLoad = 10 pF
20
td Fall time
CLoad = 10 pF
20
jcc Cycle to cycle jitter
+/-5
DATA(serial data input), D_EN (serial data enable input), D_CLK (serial data clock input)
VIH High level input voltage
VDD-0.5
-
VIL Low level input voltage
-
0.3
IIH High level input current VIH= VDD
1
IIL Low level input current VIL =0 V
-1
FD_CLK D_CLK frequency
3
RE_INT (interrupt output); WAKEUP (µC wakeup output)
VOH High level output voltage IOH = -1mA
VDD-0.5
-
VOL Low level output voltage IOL = 1mA
-
0.3
Units
V
V
ns
ns
%
V
V
µA
µA
kHz
V
V
3 Pin-out Information
Note: pin numbers have arbitrary ordering and numbering - will be defined during design
Pin Name
1 RF+
2 RF-
3 LC+
4 LC-
5 XTAL+
6 XTAL-
7 AVDD
8 AGND
9 GMC
10 RFGND
11 DGND
12 TEST1
13 TEST2
14 uC_CLK
15 RE_INT
16 WAKEUP
Type
I
I
I/O
I/O
I
O
P
P
I/O
I
P
I/O
I/O
O
O
O
Description
LNA input
LNA input
LNA tank
LNA tank
XTAL oscillator input
XTAL oscillator output
Analog positive supply
Analog negative supply
Base-Band Low Pass frequency set
RF GND
Digital negative supply
pin for test purposes
pin for test purposes
Clock output for micro controller
Interrupt at first received data block and receive end
Micro controller wake up; high during ongoing reception
Rev. A, February 2000
Page 11 of 14
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