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AS8SLC512K32Q-10 Просмотр технического описания (PDF) - Austin Semiconductor

Номер в каталоге
Компоненты Описание
производитель
AS8SLC512K32Q-10
AUSTIN
Austin Semiconductor AUSTIN
AS8SLC512K32Q-10 Datasheet PDF : 12 Pages
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Austin Semiconductor, Inc.
SRAM
AS8SLC512K32
LOW POWER CHARACTERISTICS (L Version Only)
DESCRIPTION
VCC for Retention Data
Data Retention Current
Chip Deselect to Data
Retention Time
CONDITIONS
SYMBOL MIN
VDR
2
All Inputs @ Vcc + 0.2V
or Vss + 0.2V,
CS\ = Vcc + 0.2V
VCC = 2V
VCC = 3V
ICCDR
ICCDR
tCDR
0
Operation Recovery Time
tR
20
MAX
24
32
UNITS
V
mA
mA
ns
NOTES
4
ms
4, 11
LOW VCC DATA RETENTION WAVEFORM
VCC
CS\ 1-4
tCDR
111111111222222222333333333444444444555555555666666666777777777888888888999999999000000000111111111222222222333333333444444444555555555666666666777777777888888888
DATA RETENTION MODE
4.5V
V > 2V
DR
4.5V
V
DR
tR
111111111222222222333333333444444444555555555666666666777777777888888888999999999000000000111111111222222222333333333444441111111444411555552555522222222666663333333366663777774444444477774588888888855555555
NOTES
1. All voltages referenced to VSS (GND).
2. Worst case address switching.
3. ICC is dependent on output loading and cycle rates.
unloaded, and f=
1
t RC(MIN)
HZ.
The specified value applies with the outputs
4. This parameter guaranteed but not tested.
5. Test conditions as specified with output loading as
shown in Fig. 1 & 2 unless otherwise noted.
6. t , t and t are specified with C = 5pF as in
HZCS HZOE
HZWE
L
Fig. 2. Transition is measured +/- 200 mV typical from
steady state voltage, allowing for actual tester RC time
constant.
AS8SLC512K32
Rev. 2.5 5/09
7. At any given temperature and voltage condition,
tHZCS, is less than tLZCS, and tHZWE is less than tLZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip selects and
output enable are held in their active state.
10. Address valid prior to or coincident with latest
occurring chip enable.
11. t = READ cycle time.
RC
12. Chip enable (CS\) and write enable (WE\) can initiate
and terminate a WRITE cycle.
13. I is for full 32 bit mode.
CC
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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