AS8SLC128K32P-15/883C Просмотр технического описания (PDF) - Austin Semiconductor
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AS8SLC128K32P-15/883C Datasheet PDF : 10 Pages
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Austin Semiconductor, Inc.
SRAM
AS8SLC128K32
LOW POWER CHARACTERISTICS (L Version Only)
DESCRIPTION
VCC for Retention Data
Data Retention Current
Chip Deselect to Data
Retention Time
CONDITIONS
SYMBOL MIN
VDR
2
All Inputs @ Vcc + 0.2V
or Vss + 0.2V,
CS\ = Vcc + 0.2V
VCC = 2V
VCC = 3V
ICCDR
ICCDR
tCDR
0
Operation Recovery Time
tR
20
MAX
24
32
UNITS
V
mA
mA
ns
NOTES
4
ms
4, 11
LOW VCC DATA RETENTION WAVEFORM
VCC
tCDR
CS\ 1-4
1111111122222222333333334444444455555555666666667777777788888888999999990000000011111111222222223333333344444444555555556666666677777777
DATA RETENTION MODE
4.5V
4.5V
VDR > 2V
VDR
tR
11111111222222223333333344444444555555556666666677777777888888889999999900000000111111112222222211111133333333114444442442222222555555333333355366666644444446645777777775555555
NOTES
1. All voltages referenced to VSS (GND).
2. Worst case address switching.
3. ICC is dependent on output loading and cycle rates.
unloaded, and f=
1
t RC(MIN)
HZ.
The specified value applies with the outputs
4. This parameter guaranteed but not tested.
5. Test conditions as specified with output loading as
shown in Fig. 1 & 2 unless otherwise noted.
6. tHZCS, tHZOE and tHZWE are specified with CL= 5pF as in Fig.
2. Transition is measured +/- 200 mV typical from steady
state voltage, allowing for actual tester RC time constant.
7. At any given temperature and voltage condition,
tHZCS, is less than tLZCS, and tHZWE is less than tLZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip selects and output
enable are held in their active state.
10. Address valid prior to or coincident with latest oc-
curring chip enable.
11. t = READ cycle time.
RC
12. Chip enable (CS\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
13. I is for full 32 bit mode.
CC
AS8SLC128K32
Rev. 0.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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