AS7C34098A Просмотр технического описания (PDF) - Alliance Semiconductor

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производитель

AS7C34098A

3.3 V 256 K × 16 CMOS SRAM

Alliance Semiconductor 

Write waveform 3 10

Address

CE

LB, UB

WE

DataIN

DataOUT

tAS

High Z

®

tWC

tCW

tAW

tBW

tWP

tDW

tWZ

Data undefined

AS7C34098A

tAH

tWR

Data valid

tDH

High Z

AC test conditions

- Output load: see Figure B.

- Input pulse level: GND to 3.0V. See Figure A.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

+3.3V

+3.0V

90%

90%

10%

10%

GND

2 ns

Figure A: Input pulse

DOUT

350Ω

320Ω

C11

Thevenin equivalent: DOUT 168Ω

GND

Figure B: 3.3V Output load

Notes

1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.

2 This parameter is sampled, but not 100% tested.

3 For test conditions, see AC Test Conditions, Figures A and B.

4 tCLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured ±500mV from steady-state voltage.

5 This parameter is guaranteed, but not tested.

6 WE is High for read cycle.

7 CE and OE are Low for read cycle.

8 Address valid prior to or coincident with CE transition Low.

9 All read cycle timings are referenced from the last valid address to the first transitioning address.

10 All write cycle timings are referenced from the last valid address to the first transitioning address.

11 C=30pF, except on High Z and Low Z parameters, where C=5pF.

+1.728V

8/17/04,v. 2.1

Alliance Semiconductor

P. 7 of 10

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