AS8202 Просмотр технического описания (PDF) - austriamicrosystems AG
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AS8202 Datasheet PDF : 10 Pages
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TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Pin Description
Pin
1,12,21,32,51,61,71
4,13,24,33,43,52,62,72
2
Name
Vdd
Vss
xout0
3
xin0
5
txd[0]
6
cts[0]
7
txclk[0]
8
rxer[0]
9
rxclk[0]
10
rxdv[0]
11
rxd[0]
14
txd[1]
15
cts[1]
16
txclk[1]
17
rxer[1]
18
rxclk[1]
19
rxdv[1]
20
rxd[1]
22
xout1
23
xin1
Dir Description
P
positive power supply
P
Negative power supply
O
Main clock: analog pad from oscillator / leave open
when providing external clock
I
Main clock: analog pad from oscillator / use as input
when providing external clock
OPU Transmit data channel 0
OPD Transmit enable channel 0
IPD TTP/C synchronous: Transmit clock channel 0
IPU TTP/C synchronous: Receive error channel 0
IPD TTP/C synchronous: Receive clock channel 0
IPU TTP/C synchronous: Receive data valid channel 0
IPU Receive data channel 0
OPU Transmit data channel 1
OPD Transmit enable channel 1
IPD TTP/C synchronous: Transmit clock channel 1
IPU TTP/C synchronous: Receive error channel 1
IPD TTP/C synchronous: Receive clock channel 1
IPU TTP/C synchronous: Receive data valid channel 1
IPU Receive data channel 1
O
Bus guardian clock: analog pad from oscillator / leave
open when providing external clock
I
Bus guardian clock: analog pad from oscillator / use as
input when providing external clock
25
26
27
28
29
30
31
34
35
36
37
38-42,44-50
53-60,63-70
73
74
75
76
77
78
79
80
test_se
IPD Test input, connect to Vss
stest
IPD Test input, connect to Vss
plloff
IPD PLL disable pin
ftest
IPD Test input, connect to Vss
fidis
IPD Test input, connect to Vss
resetb
I
main reset input signal, active low
time_signalb
OPU CNI control signal, CNI time signal
led[0]/microtick
OPD Configurable: either generic output port (f.e. to drive
LEDs) or timing signal TIME_TICK
led[1]/time_tick
OPD Configurable: either generic output port (f.e. to drive
LEDs) or timing signal TIME_OVERFLOW
led[2]/time_overflow OPD Configurable: either generic output port (f.e. to drive
LEDs) or timing signal TIME_OVERFLOW
mtest
IPD Test input, connect to Vss
ram_address[0:11] I
Host interface (CNI) address bus
ram_data[0:15]
I/O Host interface (CNI) data bus, tristate
ram_ceb
IPU Host interface (CNI) chip enable, active low
ram_oeb
IPU Host interface (CNI) output enable, active low
ram_web
IPU Host interface (CNI) write enable, active low
ram_readyb
OPU Host interface (CNI) transfer finish signal, active low
to Vss
P
Connect to Vss
to Vdd
IPU Connect to Vdd
high Z
Do not connect
high Z
Do not connect
I Input CMOS
IPD Input CMOS with pull down
OPD Output with pull down when tristate
I/O Input/Output CMOS tristate
IPU
Input CMOS with pull up
O
Output CMOS
OPU Output with pull up when tristate
P
Power Pin
Rev. 1.0, October 2000
Page 4 of 4
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