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AS6C1008-55TIN Просмотр технического описания (PDF) - Alliance Semiconductor
Номер в каталоге
Компоненты Описание
производитель
AS6C1008-55TIN
128K X 8 BIT LOW POWER CMOS SRAM
Alliance Semiconductor
AS6C1008-55TIN Datasheet PDF : 14 Pages
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February 2007
AS6C1008
®
128K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
V
CC
for Data Retention
SYMBOL
TEST CONDITION
V
DR
CE#
≧
V
CC
- 0.2V
or CE2
≦
0.2V
Data Retention Current
V
CC
= 1.5V
C**
I
DR
CE#
≧
V
CC
- 0.2V
or CE2
≦
0.2V
I
**
Chip Disable to Data
Retention Time
t
CDR
See Data Retention
Waveforms (below)
Recovery Time
t
R
t
RC
*
= Read Cycle Time
C=Commercial temp/I = Industrial temp**
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1)
(
CE#
controlled)
Vcc
CE#
Vcc(min.)
t
CDR
V
IH
V
DR
≧
1.5V
CE#
≧
Vcc-0.2V
MIN.
1.5
-
0
t
RC
*
TYP.
-
0.5
0
-
-
MAX.
5.5
1
3
-
-
UNIT
V
µ
µA
ns
ns
Vcc(min.)
t
R
V
IH
Low Vcc Data Retention Waveform (2)
(CE2 controlled)
Vcc
CE2
Vcc(min.)
t
CDR
V
IL
V
DR
≧
1.5V
CE2
≦
0.2V
Vcc(min.)
t
R
V
IL
02/February/07, v 1.0
Alliance Memory Inc.
Page 7 of 14
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