AS4LC4M4 Просмотр технического описания (PDF) - Austin Semiconductor
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AS4LC4M4 Datasheet PDF : 19 Pages
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16 Meg FPM DRAM
Austin Semiconductor, Inc.
AS4LC4M4
TEST MODE CYCLE11
SYMBOL
PARAMETER
tRC Random read or write cycle time
tRWC Read-modify-write cycle time
tRAC Access time from RAS\
tCAC Access time from CAS\
tAA Access time from column address
tRAS RAS\ pulse width
tCAS CAS\ pulse width
tRSH RAS\ hold time
tCSH CAS\ hold time
tRAL Column address to RAS\ lead time
tCWD CAS\ to W\ delay time
tRWD RAS\ to W\ delay time
tAWD Column address to W\ delay time
tCPWD CAS\ precharge to W\ delay time
tPC Fast Page cycle time
tPRWC Fast Page read-modify-write time
tRASP RAS\ pulse width (Fast Page Cycle)
tCPA Access time from CAS\ precharge
tOEA OE\ access time
tOED OE\ to data delay
tOEH OE\ command hold time
-60
MIN MAX
115
160
65
20
35
65
10K
20
10K
20
65
35
45
90
60
65
45
90
65 200K
40
20
20
20
-70
MIN MAX
UNITS NOTES
ns
ns
ns 3, 4, 10, 12
ns 3, 4, 5, 12
ns 3, 10 ,12
ns
ns
ns
ns
ns
ns
7
ns
7
ns
7
ns
ns
ns
ns
ns
3
ns
ns
ns
NOTES:
1. An initial pause of 200us is required after power-up followed by an 8 RAS\-only refresh or CAS\-before-RAS\ refresh cycles before proper device operation is achieved.
2. VIH(MIN) and VIL(MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH(MIN) and VIL(MAX) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 1 TTL loads and 100pF.
4. Operation within the tRCD(MAX) limit insures that tRAC(MAX) and be met. tRCD(MAX) is specified as a reference point only. If tRCD is greater than the specified tRCD(MAX) limit, then access time is
controlled exclusively by tCAC.
5. Assumes that tRCD > tRCD(MAX).
6. tOFF(MIN) and tOEZ(MAX) define the time at which the output achieves the open circuit condition and are not referenced VOH or VOL.
7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS(MIN), the cycle is an early write cycle and the data
output will remain high impedance for the duration of the cycle. If tCWD > tCWD(MIN), tRWD > tRWD(MIN) and tAWD > tAWD(MIN), then the cycle is a read-modify-write cycle and the data output will
contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to CAS\ falling edge in early write cycles and to W\ falling edge in read-modify-write cycles.
10. Operation within the tRAD(MAX) limit insures that tRAC(MAX) can be met. tRAD(MAX) is specified as a reference point only. If tRAD is greater than the specified tRAS(MAX) limit, then access time is
controlled by tAA.
11. These specifications are applied in the test mode.
12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified
value in this data sheet.
13. If tRASS > 100 us, then RAS\ precharge time must use tRPS instead of tRP.
14. For RAS\-only refresh and burst CAS\-before-RAS\ refresh mode, 2048 cycles of burst refresh must be executed within 32ms before and after self refresh, in order to meet refresh specification.
15. For distributed CAS\-before-RAS\ with 15.6us interval CAS\-before-RAS\ refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
AS4LC4M4
Rev. 0.3 7/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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