AS4LC4M16DG-6S/IT(2002) Просмотр технического описания (PDF) - Austin Semiconductor
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AS4LC4M16DG-6S/IT Datasheet PDF : 25 Pages
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Austin Semiconductor, Inc.
DRAM
AS4LC4M16
CAPACITANCE2
PARAMETER
Input Capacitance: Address Pins
Input Capacitance: RAS\, CAS\, WE\, OE\
Input/Output Capacitance: DQ
SYM
CI1
CI2
CI0
MAX
5
7
7
UNIT
pF
pF
pF
AC ELECTRICAL CHARACTERISTICS5,6,7,8,9,10,11,12
(VCC = +3.3V ±0.3V)
DESCRIPTION
Access time from column address
Column-address setup to CAS\ precharge
Column-address hold time (referenced to RAS\)
Column-address setup time
Row-address setup time
Column address to WE\ delay time
Access time from CAS\
Column-address hold time
CAS\ pulse width
CAS\ LOW to "Don't Care" during Self Refresh
CAS\ hold time (CBR Refresh)
Last CAS\ going LOW to first CAS\ to return HIGH
CAS\ to output in Low-Z
Data output hold after CAS\ LOW
CAS\ precharge time
Access time from CAS\ precharge
CAS\ to RAS\ precharge time
CAS\ hold time
CAS\ setup time (CBR Refresh)
CAS\ to WE\ delay time
WRITE command to CAS\ lead time
Data-in hold time
Data-in setup time
Output disable
Output enable time
OE\ hold time from WE\ during
READ-MODIFY-WRITE cycle
SYMBOL
tAA
tACH
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHD
tCHR
tCLCH
tCLZ
tCOH
tCP
tCPA
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
tDS
tOD
tOE
-5
MIN MAX
25
12
38
0
0
42
13
8
8 10,000
15
8
5
0
3
8
28
5
38
5
28
8
8
0
0
12
12
-6
MIN MAX
30
15
45
0
0
49
15
10
10 10,000
15
10
5
0
3
10
35
5
45
5
35
10
10
0
0
15
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
28
28
18
29
28
30, 32
4, 31
31
29
13, 33
29
31
31
4, 28
18, 28
31
19, 29
19, 29
24, 25
20
tOEH
8
10
ns
25
OE\ HIGH hold time from CAS\ HIGH
OE\ HIGH pulse width
OE\ LOW to CAS\ HIGH setup time.
Output buffer turn-off delay
tOEHC
5
10
ns
tOEP
5
5
ns
tOES
4
5
ns
tOFF
0
12
0
15
ns 17, 24, 29
OE\ setup prior to RAS\ during HIDDEN REFRESH cycle
tORD
0
0
ns
AS4LC4M16
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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