AS4C4M4DG-6/XT Просмотр технического описания (PDF) - Austin Semiconductor

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AS4C4M4DG-6/XT

4M x 4 CMOS DRAM WITH FAST PAGE MODE, 5 VOLT

Austin Semiconductor 

16 Meg FPM DRAM

Austin Semiconductor, Inc.

AS4C4M4

NOTES (continued):

8. Either t or t must be satisfied for a read cycle.

RCH

RRH

9. These parameters are referenced to CAS\ falling edge in early write cycles and to W\ falling edge in read-modify-write

cycles.

10. Operation within the t (MAX) limit insures that t (MAX) can be met. t (MAX) is specified as a reference point only.

RAD

RAC

RAD

If tRAD is greater than the specified tRAS(MAX) limit, then access time is controlled by tAA.

11. These specifications are applied in the test mode.

12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters

should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

13. If t > 100 us, then RAS\ precharge time must use t instead of t .

RASS

RPS

RP

14. For RAS\-only refresh and burst CAS\-before-RAS\ refresh mode, 2048 cycles of burst refresh must be executed within

32ms before and after self refresh, in order to meet refresh specification.

15. For distributed CAS\-before-RAS\ with 15.6us interval CAS\-before-RAS\ refresh should be executed with in 15.6us

immediately before and after self refresh in order to meet refresh specification.

READ CYCLE

AS4C4M4

Rev. 1.1 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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