AS1541 Просмотр технического описания (PDF) - austriamicrosystems AG
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AS1541 Datasheet PDF : 20 Pages
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AS1539/AS1541
Data Sheet - Electrical Characteristics
Table 3. Electrical Characteristics
Symbol
CMOS Digital I/O
Parameter
Condition
Min Typ Max Unit
VIH
Input High Logic Level
+VDD
x 0.7
+VDD
+ 0.5
V
VIL
Input Low Logic Level
-0.3
+VDD
x 0.3
V
VOL
Output Low Logic Level
IIH
Input High Leakage Current
3mA sink current
VIH = +VDD
0.4
V
1
µA
IIL
Input Low Leakage Current
VIL = GND
-1
µA
Data Format
Straight binary
Power Supply Requirements
+VDD
Power Supply Voltage
Specified performance
PD = 00 Full Power-Down
2.7
5.25 V
0.04 1.2
Analog Current in Static Mode, PD = 01 Internal Ref. OFF, ADC ON
3.6V
PD = 10 Internal Ref. ON, ADC OFF
390 475
µA
440 475
IQSTAT
PD = 11 Internal Ref. ON, ADC ON
PD = 00 Full Power-Down
765 825
0.04 1.5
Analog Current in Static Mode, PD = 01 Internal Ref. OFF, ADC ON
5.25V
PD = 10 Internal Ref. ON, ADC OFF
430 485
µA
465 500
PD = 11 Internal Ref. ON, ADC ON
820 870
Quiescent Current at Full PD = 01 Internal Ref. OFF, ADC ON
Speed, 3.6V
PD = 11 Internal Ref. ON, ADC ON
IQ
Quiescent Current at Full PD = 01 Internal Ref. OFF, ADC ON
Speed, 5.25V
PD = 11 Internal Ref. ON, ADC ON
500 550 µA
850 925
650 725
µA
915 1100
1. Guaranteed by design and characterized on sample base.
2. THD measure out to 5th harmonic.
Timing Characteristics
+VDD = +2.7 to 5.25V, TAMB = -40 to +85ºC (unless otherwise specified). All values referenced to VIHMIN and VILMAX
levels.
Table 4. Timing Characteristics
Symbol
fSCL
tBUF
THOLDSTART
tLOW
tHIGH
TSETUPSTART
TSETUPDATA
THOLDDATA
TRISESCLK1
TRISESCLK11
Parameter
SCL Frequency
Bus Free Time Between
STOP and START Conditions
Hold Time for Repeated
START Condition
SCL Low Period
SCL High Period
Setup Time for Repeated
START Condition
Data Setup Time
Data Hold Time
SCL Rise Time
SCL Rise Time after
Repeated START Condition
and After an ACK Bit
Condition
Min Typ Max Unit
0.1
3.4 MHz
1.3
µs
160
ns
50
75 ns
50
75 ns
100
ns
10
ns
70
ns
10
40 ns
10
80 ns
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Revision 1.02
5 - 20
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