AS1120 Просмотр технического описания (PDF) - austriamicrosystems AG

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AS1120

46-Segment LCD Driver

austriamicrosystems AG 

AS1120

Datasheet - Detailed Description

Asynchronous Mode

Data can be preloaded into the AS1120 shift register and then activated via a LOAD pulse. To preload the shift register

the LOAD signal must stay high as all 46 data bits are clocked into the internal shift register at the rising edge of CLKIN

(see Figure 5).

Note: In asynchronous mode, a clock signal must be applied on pin BPLIN. Asynchronous mode does not support

the use of the AS1120 internal clock.

Figure 5. Timing Diagram for Preloading the Shift Register

46 CLKIN Cycles

LOAD

LOAD Always High

DATAIN

CLKIN

BPLIN

X X LD45 LD45LD45

LD10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0

Stop

To update the LCD display the LOAD signal must be held low for at least 8 periods of the clock applied at BPLIN, and

CLKIN must be set to low. Note that since BPLIN is normally asynchronous in respect to LOAD, it is advisable to keep

LOAD low for 8+1 BPLIN cycles. The display will be updated at the 8th BPLIN rising edge while LOAD is Low.

In case of internal BPLIN generation through the internal oscillator BPLIN = fOSC/16.

Figure 6. Timing Diagram for Updating the Display in Asynchronous Mode

LOAD

9 BPLIN Cycles

DATAIN

CLKIN

BPLIN

Display

X X X XX X X X X X X X X X X X X

CLKIN Always High

Update

R/C Oscillator and Backplane Generation

The AS1120 can generate the backplane signal using an internal R/C oscillator, or an externally generated backplane

signal can be supplied.

When cascading multiple AS1120 devices (see Figure 8 on page 9), only the first device should have the oscillator run-

ning; the other devices must use pin BPLIN to regenerate the backplane signal and to synchronize their LCD output

segments with the common backplane.

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Revision 1.05

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