APW7065 Просмотр технического описания (PDF) - Anpec Electronics

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APW7065

Synchronous Buck PWM Controller

Anpec Electronics 

APW7065

Functional Description (Cont.)

Soft-Start (Cont.)

and prevents the large peak current to charge output

capacitor.

Voltage(V)

VCC

V OUT

- The MOSFET’s RDS(ON) is varied by temperature and

gate to source voltage, the user should de-

term ine the maximum RDS(ON) in manufacturer’s

datasheet.

- The minimum Vocset should be used in the above

equation.

- Note that the ILIMIT is the current flow through the

lower MOSFET; ILIMIT must be greater than maxi-

mum output current add the half of inductor ripple

current.

Shutdown and Enable

t1

Voltage(V)

t2 t3

Figure 1.

Time

FB

Pulling the COMP voltage to GND by an open drain

transistor, shown in typical application circuit,

shutdown the APW7065 PWM controller. In shutdown

mode, the UGATE and LGATE turn off and pull to

PHASE and GND respectively.

12.5mV

16/Fosc

Time

Figure 2.

Over-Current Protection

The over-current protection monitors the output current

by using the voltage drop across the lower MOSFET’s

RDS(ON) and this voltage drop will be compared with the

internal 0.27V reference voltage. If the voltage drop

across the lower MOSFET’s RDS(ON) is larger than

0.27V, an over-current condition is detected. The

threshold of the over current limit is given by:

ILimit

=

0.27

R DS( ON)

For the over-current is never occurred in the normal

operating load range; the variation of all parameters in

the above equation should be determined.

Under Voltage Protection

The FB pin is monitored during converter operation by

the internal Under Voltage (UV) comparator. If the FB

voltage drops below 50% of the reference voltage (50%

of 0.8V = 0.4V), a fault signal is internally generated,

and the device turns off both high-side and low-side

MOSFET and the converter’s output is latched to be

floating.

Application Information

Output Voltage Selection

The output voltage can be programmed with a resistive

divider. Use 1% or better resistors for the resistive

divider is recommended. The FB pin is the inverter

input of the error amplifier, and the reference voltage

is 0.8V. The output voltage is determined by:

V OUT

= 0.8

×  1 +

R OUT

R GND



Where R is the resistor connected from V to FB

OUT

OUT

and RGND is the resistor connected from FB to GND.

Copyright © ANPEC Electronics Corp.

11

Rev. A.1 - Feb., 2006

www.anpec.com.tw

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