HM-6516 Просмотр технического описания (PDF) - Intersil
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HM-6516 Datasheet PDF : 6 Pages
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HM-6516
The write cycle is initiated on the falling edge of E (T = 0),
which latches the address information in the on-chip
registers. If a write cycle is to be performed where the output
is not to become active, G can be held high (inactive).
TDVWH and TWHDX must be met for proper device opera-
tion regardless of G. If E and G fall before W falls (read
mode), a possible bus conflict may exist. If E rises before W
rises, reference data setup and hold times to the E rising
edge. The write operation is terminated by the first rising edge
of W (T = 2) or E (T = 3). After the minimum E high time
(TEHEL), the next cycle may begin. If a series of consecutive
write cycles are to be performed, the W line may be held low
until all desired locations have been written. In this case, data
setup and hold times must be referenced to the rising of E.
Typical Performance Curve
VCC = 2.0V
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-55 -35 -15 5
25 45 65 85 105 125
FIGURE 3. TYPICAL ICCDR vs TA
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