HM-6516 Просмотр технического описания (PDF) - Intersil
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HM-6516 Datasheet PDF : 6 Pages
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HM-6516
Timing Waveforms
(11)
A
TAVEL
(2)
TAVQV
(12)
TELAX
VALID ADD
(10)
TEHEL
E
HIGH
W
(5)
TEHQZ
DQ
G
(9)
TELEH
(1)
(3) TELQV
TELQX
(6)
TGLQV
(7)
TGLQX
(18)
TELEL
(11)
TAVEL
NEXT
ADD
(10)
TEHEL
(5)
TEHQZ
VALID DATA OUT
TGHQZ
(8)
TIME
REFERENCE
-1
0
1
2
3
4
5
FIGURE 1. READ CYCLE
The address information is latched in the on-chip registers
on the falling edge of E (T = 0), minimum address setup and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1), the outputs become
enabled but data is not valid until time (T = 2), W must
remain high throughout the read cycle. After the data has
been read, E may return high (T = 3). This will force the out-
put buffers into a high impedance mode at time (T = 4). G is
used to disable the output buffers when in a logical “1” state
(T = -1, 0, 3, 4, 5). After (T = 4) time, the memory is ready for
the next cycle.
Timing Waveforms (Continued)
(11)
TAVEL
(12)
TELAX
(11)
TAVEL
A
VALID ADD
NEXT ADD
(10)
TEHEL
(9)
TELEH
(18)
TELEL
(10)
TEHEL
E
(14)
TWLEH
(13)
TWLWH
W
(15)
TELWH
(16)
TDVWH
(17)
TWHDX
DQ
G HIGH
VALID DATA IN
TIME
REFERENCE
-1
0
1
2
3
4
5
FIGURE 2. WRITE CYCLE
6-5
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