AOZ1020 Просмотр технического описания (PDF) - Alpha and Omega Semiconductor
Номер в каталоге
Компоненты Описание
производитель
AOZ1020 Datasheet PDF : 15 Pages
| |||
AOZ1020
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected
crossover frequency. C2 can is selected by:
CC = 2----π-----×-----R1---.-C-5----×-----f--p---1-
Equation above can also be simplified to:
CC = C-----O--R---×--C---R-----L-
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
Thermal Management and Layout
Consideration
In the AOZ1020 buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the LX
pin, to the filter inductor, to the output capacitor and load,
and then return to the input capacitor through ground.
Current flows in the first loop when the high-side switch is
on. The second loop starts from inductor, to the output
capacitors and load, to the low-side NMOSFET. Current
flows in the second loop when the low-side NMOSFET is
on.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input capaci-
tor, output capacitor, and PGND pin of the AOZ1020.
In the AOZ1020 buck regulator circuit, the major power
dissipating components are the AOZ1020 and the output
inductor. The total power dissipation of converter circuit
can be measured by input power minus output power.
Ptotal_loss = VIN × IIN – VO × IO
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor.
Pinductor_loss = IO2 × Rinductor × 1.1
The actual junction temperature can be calculated with
power dissipation in the AOZ1020 and thermal imped-
ance from junction to ambient.
Tjunction = (Ptotal_loss–Pinductor_loss) × ΘJA
The maximum junction temperature of AOZ1020 is
150°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ1020 under different ambient
temperature.
The thermal performance of the AOZ1020 is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC
will operate under the recommended environmental
conditions.
The AOZ1020A is a standard SO-8 package. Layout tips
are listed below for the best electric and thermal
performance. Figure 3 illustrates a PCB layout example
of the AOZ1020A.
1. Do not use thermal relief connection to the VIN
and the PGND pin. Pour a maximized copper area
to the PGND pin and the VIN pin to help thermal
dissipation.
2. Input capacitor should be connected as close as
possible to the VIN pin and the PGND pin.
3. A ground plane is suggested. If a ground plane is
not used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin noise
coupling to the AGND pin.
4. Make the current trace from the LX pin to L to CO to
the PGND as short as possible.
5. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
6. The LX pin is connected to internal PFET drain. It is
a low resistance thermal conduction path and the
most noisy switching node. Connect a copper plane
to the LX pin to help thermal dissipation. This
copper plane should not be too large otherwise
switching noise may be coupled to other parts of
the circuit.
7. Keep sensitive signal traces far away from the LX
pin.
Rev. 1.5 December 2010
www.aosmd.com
Page 11 of 15
Share Link: 