AOZ1020 Просмотр технического описания (PDF) - Alpha and Omega Semiconductor
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AOZ1020 Datasheet PDF : 15 Pages
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AOZ1020
For lower output ripple voltage across the entire operat-
ing temperature range, X5R or X7R dielectric type of
ceramic, or other low ESR tantalum are recommended to
be used as output capacitors.
In a buck converter, output capacitor current is continuous.
The RMS current of output capacitor is decided by the
peak to peak inductor ripple current. It can be calculated
by:
ICO_RMS
=
--Δ----I--L--
12
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and induc-
tor ripple current is high, the output capacitor could be
overstressed.
Loop Compensation
The AOZ1020 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is the dominant pole can
be calculated by:
fp1 = -2---π-----×-----C--1--O------×-----R----L-
The zero is an ESR zero due to output capacitor and its
ESR. It is can be calculated by:
fZ1 = -2---π-----×-----C----O-----1-×----E-----S----R-----C----O--
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the
converter control loop transfer function to get the desired
gain and phase. Several different types of compensation
network can be used for the AOZ1020. In most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ1020, FB pin and COMP pin are the inverting
input and the output of internal error amplifier. A series R
and C compensation network connected to COMP
provides one pole and one zero. The pole is:
fp2 = 2----π-----×-----C--G--C---E--×--A---G-----V----E---A--
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
GVEA is the error amplifier voltage; and
C2 is compensation capacitor in Figure 1.
The zero given by the external compensation network,
capacitor C2 and resistor R3, is located at:
fZ2 = -2---π-----×-----C---1-C-----×-----R-----C--
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where control loop has unity gain.
The crossover is the also called the converter bandwidth.
Generally a higher bandwidth means faster response to
load transient. However, the bandwidth should not be too
high because of system stability concern. When design-
ing the compensation loop, converter stability under all
line and load condition must be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. The
AOZ1020 operates at a frequency range from 400kHz
to 600kHz. It is recommended to choose a crossover
frequency equal or less than 40kHz.
fC = 40kHz
The strategy for choosing RC and CC is to set the
cross over frequency with RC and set the compensator
zero with CC. Using selected crossover frequency, fC,
to calculate R3:
RC = fC × V--V---F-O--B-- × G-----2E----πA-----××-----CG----2C----S--
where;
where fC is desired crossover frequency. For best performance,
fC is set to be about 1/10 of switching frequency,
VFB is 0.8V,
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V, and
GCS is the current sense circuit transconductance, which is
5.64 A/V
Rev. 1.5 December 2010
www.aosmd.com
Page 10 of 15
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