AOZ1012DI Просмотр технического описания (PDF) - Alpha and Omega Semiconductor
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AOZ1012DI Datasheet PDF : 17 Pages
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where CO is output capacitor value and ESRCO is the
Equivalent Series Resistor of output capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the
switching frequency dominates. Output ripple is mainly
caused by capacitor value and inductor ripple current.
The output ripple voltage calculation can be simplified
to:
∆VO
=
∆I L
×
8×
1
f × CO
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided
by capacitor ESR and inductor ripple current. The
output ripple voltage calculation can be further
simplified to:
∆VO = ∆I L × ESRCO
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum are
recommended to be used as output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It
can be calculated by:
I CO _ RMS
=
∆I L
12
Usually, the ripple current rating of the output capacitor
is a smaller issue because of the low current stress.
When the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
Loop Compensation
AOZ1012D employs peak current mode control for easy
use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole and can
be calculated by:
^lwNMNOa
f p1
=
2π
1
× CO
×
RL
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
fZ1
=
2π
1
× CO ×
ESRCO
Where CO is the output filter capacitor;
RL is load resistor value;
ESRCO is the equivalent series resistance of
output capacitor;
The compensation design is actually to shape the
converter close loop transfer function to get desired
gain and phase. Several different types of compensation
network can be used for AOZ1012D. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a
stable high-bandwidth control loop.
In AOZ1012D, FB pin and COMP pin are the inverting
input and the output of internal transconductance error
amplifier. A series R and C compensation network
connected to COMP provides one pole and one zero.
The pole is:
f p2
=
2π
GEA
× CC × GVEA
Where GEA is the error amplifier transconductance,
which is 200·10-6 A/V;
GVEA is the error amplifier voltage gain,
which is 500 V/V;
CC is compensation capacitor;
The zero given by the external compensation network,
capacitor CC and resistor RC, is located at:
fZ2
=
2π
1
× CC
×
RC
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The
system crossover frequency is where control loop has
unity gain. The crossover frequency is the also called
the converter bandwidth. Generally a higher bandwidth
means faster response to load transient. However, the
bandwidth should not be too high because of system
stability concern. When designing the compensation
April 2006
www.aosmd.com
Page 11 of 17
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