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AN8028 Просмотр технического описания (PDF) - Panasonic Corporation

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AN8028 Datasheet PDF : 13 Pages
First Prev 11 12 13
Voltage Regulators
AN8028
s Application Notes (continued)
[1] Operation descriptions (continued)
8. Timer latch (continued)
VO
Power supply
output voltage
0
IDS
Power MOSFET
current
0
Power supply stop
Time
Power supply stop
Time
VOVP
TIM/OVP
terminal voltage
0
Power supply stop
OVP
VTH = 7.3 V (typ.)
Figure 10. Timer latch basic operation
Time
9. Output block
In order to drive the power MOSFET which is a capacitive load at high speed, this IC is adopting the totem pole
(push-pull) type output circuit which performs the sink and source of the current with the NPN transistor as
shown in figure 11.
The maximum sink/source current is ±0.1 A (DC) and the current at peak is ±1.0 A (peak). The circuit is
provided with the sink capability even if the supply voltage VCC is under the stop voltage so that it turns off the
power MOSFET without fail.
The peak current capability is mainly required
and a particularly too large current is not required
constantly.
Because the power MOSFET becomes a ca-
pacitive load for the output, a large peak current
is required for driving it at a high speed. How-
ever, after the charge and discharge, a particularly
Schottky barrier
diode
large current is not required to keep such condi-
tion. In the case of this IC, the peak current capa-
bility of ±1 A is ensured by taking a capacitance
value of the power MOSFET used into account.
Figure 11
The parasitic LC of the power MOSFET may produce ringing to decrease the output pin under the GND
potential. When the voltage decrease of the output pin becomes larger than the voltage drop of diode and its
voltage becomes negative, the parasitic diode consisting of the substrate and collector of the output NPN turns
on. This phenomenon can cause the malfunction of device. In such a case, the Schottky barrier diode should be
connected between the output and GND.
11

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