AN18207A Просмотр технического описания (PDF) - Panasonic Corporation

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AN18207A

Tuner IC for home-audio stereo set

Panasonic Corporation 

AN18207A

„ Electrical Characteristics (Reference values for design) (continued) at VCC1 = 9.0 V , VCC2 = 10 V

Notes) Ta = 25°C±2°C unless otherwise specified.

The characteristics listed below are reference values derived from the design of the IC and are not guaranteed by inspection.

If a problem does occur related to these characteristics, we will respond in good faith to user concerns.

B

No.

Parameter

Symbol

Conditions

Reference values

Unit Notes

Min Typ Max

I2C Interface (Fast-mode)

35 SCL maximum frequency

36 Hysteresis of Schmitt trigger inputs 1

fSCL

—

Vhys1 5 V mode Pin 13 : GND

— — 400 kHz *2

0.25 — — V *2

37 Hysteresis of Schmitt trigger inputs 1 Vhys2 3 V mode Pin 13 : OPEN

0.15 — — V *2

38 Output fall time from VIHmin to VILmax

39

Pulse width of spikes which must be

suppressed by the input filter

Tof Bus capacitance : 10 pF to 400 pF 20 + ⎯ 250 ns *2

Ip < 6 mA

0.1Cb

tSP

—

0

— 50 ns *2

40 Capacitance for each I/O pin

Ci Bus capacitance : 10 pF to 400 pF — — 10 pF *2

41 Hold time (repeated)

42 Low period of the SCL clock

43 High period of the SCL clock

44

Set-up time for a repeat START

condition

tHD:STA

The first clock pulse is generated

after tHD:STA

0.6

—

— μs *2

tLOW

⎯

1.3 ⎯ ⎯ μs *2

tHIGH

⎯

0.6 ⎯ ⎯ μs *2

tSU:STA

⎯

0.6 ⎯ ⎯ μs *2

45 Data hold time

tHD:DAT

⎯

0

⎯ 0.9 μs *2

46 Data set-up time

tSU:DAT

⎯

100 ⎯ ⎯ ns *2

47 Rise time of both SDA and SCL signals tr

⎯

20 +

0.1Cb

⎯

300

ns

*2

48 Fall time of both SDA and SCL signals

tf

⎯

20 +

0.1Cb

⎯

300

ns

*2

49 Set-up time of STOP condition

tSU:STO

⎯

0.6 ⎯ ⎯ μs *2

50

Bus free time between a STOP and

START condition

tBUF

⎯

1.3 ⎯ ⎯ μs *2

51 Capacitive load for each bus line

Cb

⎯

⎯ ⎯ 400 pF *2

SDC00078AEB

12

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