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ST7 S/W IMPLEMENTATION OF I2C BUS MASTER

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ST7 S/W IMPLEMENTATION OF I2C BUS MASTER

2.2 INITIATING A COMMUNICATION

To initiate an I2C communication, first a start condition has to be generated and then the se-

lected slave address has to be sent, both by the master.

Here, this action is done by calling the function I2Cm_Start() followed by the sending of the

slave address with the least significant bit correctly set (0:transmission, 1:reception).

As the slave here is an EEPROM, two addresses have to be sent by the master to the slave:

the address of the slave and the address where you want to write or read into the EEPROM

(refer to Section 3: Communication frames).

2.3 SENDING A DATA BYTE ON THE I2C BUS

To transmit a new data byte from the ST72324, the addresses or data bytes previously trans-

mitted have to be completed correctly. This previous byte transmission check is done with the

reception of an acknowledge condition by the master. If an error is detected (AF: Acknowledge

Failure), the AF bit of the created I2C_SR2 register is cleared and the transmission is re-

started from the START condition.

When the previous data transmission is over, the application writes the new data byte to be

transmitted. The data to transmit is put on the created I2C_DR register and is sent bit by bit

through PADR (PA6=SDA), MSB first.

All the data to send to the slave (and the addresses too) are stored in a table.

2.4 RECEIVING A DATA BYTE ON THE I2C BUS

To receive a new data byte, the previous data byte to receive has to be completed correctly.

This byte reception check is done with the sending of an acknowledge condition by the

master. An AF can’t occur on the master side because it’s the master that sends the acknowl-

edge condition. If there is a problem with the reception of this acknowledge, it’s up to the slave

to manage this problem.

The frame in this case (master receiver) is: the master after sending the first Start condition

and the two addresses, has to resend a Start condition followed by the address of the

EEPROM, but this time with the least significant bit at 1 to make the slave understand it’s

waiting for the data (refer to Section 3: Communication frames).

When the master is receiver, after receiving the last data, it has to generate a non acknowl-

edge condition to be able to generate the STOP condition afterwards.

Note: There is no need to clear the ACK bit to disable acknowledgement before receiving the

second last byte or set the STOP bit before receiving the last byte (as is necessary in ST7

MCUs with a dedicated I2C peripheral), because here Acknowledgement and Stop condition

generation is under software control, while in the I2C Peripheral it is under hardware control.

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