AN-136 Просмотр технического описания (PDF) - Integrated Device Technology
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AN-136 Datasheet PDF : 12 Pages
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A NEW GENERATION OF TAG SRAMS—THE IDT71215 AND IDT71216
APPLICATION NOTE AN-136
ADDR
PowerPC
TA
TT1
A0 - A28
A13 - A26
IDT71216
TAG RAM
A1 - A12
TAG (11:0)
ADDR (13:0)
MATCH
RESET
3
STATUSOUT
TA
3
STATUSIN
TT1
VCC
TAOE
TAH
CS2
TAIN
CS1
OES
SFUNC
WES
WET
OET
PWRDN
VARIOUS CONTROL SIGNALS
CHIP SET
MATCH
STATUS
STATUS
TAOE
TAH
WES
WET
OET
PWRDN
TA
A13 - A28
DATA RAMS
ADDR
CACHE READ
and WRITE
64K x 18
BURST
SRAM
I/Os
MAIN MEMORY READ/WRITE
72
DATA
DH0 - DH31, DL0 - DL31, and DP0 - DP7
Figure 12: PowerPC / 71216 Example of 512 KB Cache
Figure 12 shows a 512KB cache implementation for the
PowerPC, using the full address range of the 71216. This
example uses a bussed TA implementation shown in Figure 9.
The tag size is sufficient to support 2GB of cacheable main
memory.
3176 dr w 12
10
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