CXB1583Q Просмотр технического описания (PDF) - Sony Semiconductor
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CXB1583Q Datasheet PDF : 23 Pages
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CXB1583Q
Pin
No.
Symbol
Type
Typical pin
I/O voltage
VCCG
Equivalent circuit
74
ALTENB∗
TTL
input
TTL level
TTL-IN
VEET
VCCG
75 TPGEN∗
TTL
input
TTL level
TTL-IN
VEET
VCCG
76 TXSER
TTL
input
TTL level
TTL-IN
VEET
VCCG
77
REFCLK
TTL
input
TTL level
TTL-IN
VEET
Description
Alternate disparity test
pattern generation
enable.
When ALTENB∗ is set
to low with TPGEN∗
low, K28.5 (+K28.5,
–K28.5) is generated
for the data stream
output. When this pin
is high, +K28.5 is
VEEG generated.
Test pattern
generation enable.
When this pin is low,
+K28.5 (ALTENB∗:
high) or ±K28.5
(ALTENB∗: low) is
generated for the
data stream output.
VEEG
Transmit serial data
selector.
When this pin is high,
the serial data input
from TXSIN is output
from SDOUT and the
serialized PDI0 to 9
signals are output
from TXSOUT.
VEEG
Transmit byte clock.
This clock is used to
take the PDI0 to 9
signals in the TXPLL.
The RXPLL takes the
frequency from
REFCLK when
LCKREF∗ is low.
REFCLK is necessary
after LCKREF∗ is set
to high and the
VEEG RXPLL is locked to
the serial data.
– 10 –
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