AMD-X5-133 Просмотр технического описания (PDF) - Advanced Micro Devices

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AMD-X5-133

Am5X86™ Microprocessor Family

Advanced Micro Devices 

PRELIMINARY

AMD

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SMM Base Slot Offset ............................................................................................................. 48

SRAM Usage .......................................................................................................................... 48

SMRAM Location .................................................................................................................... 49

SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode

with Caching Enabled During SMM.......................................................................................... 50

SMM Timing in Systems Using Non-Overlaid Memory Spaces and Write-Back Mode with

Caching Enabled During SMM ................................................................................................. 50

SMM Timing in Systems Using Non-Overlaid Memory Spaces and Write-Back Mode with

Caching Disabled During SMM ................................................................................................ 50

SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode with

Caching Enabled During SMM ................................................................................................. 51

SMM Timing in Systems Using Overlaid Memory Spaces and Write-Through Mode with

Caching Disabled During SMM ................................................................................................ 51

SMM Timing in Systems Using Overlaid Memory Spaces and Configured in

Write-Back Mode...................................................................................................................... 51

CLK Waveforms ...................................................................................................................... 61

Output Valid Delay Timing ...................................................................................................... 61

Maximum Float Delay Timing .................................................................................................. 62

PCHK Valid Delay Timing ....................................................................................................... 62

Input Setup and Hold Timing ................................................................................................... 63

RDY and BRDY Input Setup and Hold Timing ........................................................................ 63

TCK Waveforms ...................................................................................................................... 64

Test Signal Timing Diagram .................................................................................................... 64

LIST OF TABLES

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Clocking Options ....................................................................................................................... 1

EADS Sample Time ................................................................................................................ 14

Cache Line Organization ......................................................................................................... 19

Legal Cache Line States ......................................................................................................... 19

MESI Cache Line Status ......................................................................................................... 20

Key to Switching Waveforms ................................................................................................... 22

WBINVD/INVD Special Bus Cycles ......................................................................................... 33

FLUSH Special Bus Cycles ..................................................................................................... 34

Pin State during Stop Grant Bus State .................................................................................... 37

SMRAM State Save Map ........................................................................................................ 43

SMM Initial CPU Core Register Settings ................................................................................. 45

Segment Register Initial States ............................................................................................... 45

SMM Revision Identifier .......................................................................................................... 46

SMM Revision Identifier Bit Definitions ................................................................................... 46

HALT Auto Restart Configuration ............................................................................................ 47

I/O Trap Word Configuration ................................................................................................... 47

Test Register TR4 Bit Descriptions ......................................................................................... 53

Test Register TR5 Bit Descriptions ......................................................................................... 53

CPU ID Codes ......................................................................................................................... 56

CPUID Instruction Description ................................................................................................. 56

Thermal Resistance (°C/W) θJC and θJA for the Am5X86 CPU in 168-Pin PGA Package ....... 65

Maximum TA at Various Airflows in °C .................................................................................... 65

Maximum TA for SQFP Package by Clock Frequency ............................................................. 65

Am5X86 Microprocessor

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