AMD-X5-133 Просмотр технического описания (PDF) - Advanced Micro Devices

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AMD-X5-133

Am5X86™ Microprocessor Family

Advanced Micro Devices 

AMD

PRELIMINARY

Table of Contents

1 Connection Diagrams and Pin Designations ......................................................................................... 8

1.1 168-Pin PGA (Pin Grid Array) Package .......................................................................................... 8

1.2 168-Pin PGA Designations (Functional Grouping) ......................................................................... 9

1.3 208-Pin SQFP (Shrink Quad Flat Pack) Package ........................................................................ 10

1.4 208-Pin SQFP Designations (Functional Grouping) ..................................................................... 11

2 Logic Symbol ...................................................................................................................................... 12

3 Pin Description .................................................................................................................................... 13

4 Functional Description ........................................................................................................................ 18

4.1 Overview ....................................................................................................................................... 18

4.2 Memory ......................................................................................................................................... 18

4.3 Modes of Operation ...................................................................................................................... 18

4.3.1 Real mode ........................................................................................................................... 18

4.3.2 Virtual mode ........................................................................................................................ 18

4.3.3 Protected mode ................................................................................................................... 18

4.3.4 System Management mode ................................................................................................ 18

4.4 Cache Architecture ....................................................................................................................... 18

4.4.1 Write-Through Cache .......................................................................................................... 18

4.4.2 Write-Back Cache ............................................................................................................... 18

4.5 Write-Back Cache Protocol ........................................................................................................... 19

4.5.1 Cache Line Overview .......................................................................................................... 19

4.5.2 Line Status and Line State .................................................................................................. 19

4.5.2.1 Invalid ......................................................................................................................... 19

4.5.2.2 Exclusive .................................................................................................................... 19

4.5.2.3 Shared ....................................................................................................................... 19

4.5.2.4 Modified ..................................................................................................................... 19

4.6 Cache Replacement Description .................................................................................................. 20

4.7 Memory Configuration ................................................................................................................... 20

4.7.1 Cacheability ......................................................................................................................... 20

4.7.2 Write-Through/Write-Back ................................................................................................... 20

4.8 Cache Functionality in Write-Back mode ...................................................................................... 20

4.8.1 Processor-Initiated Cache Functions and State Transitions ............................................... 20

4.8.2 Snooping Actions and State Transitions ............................................................................. 21

4.8.2.1 Difference between Snooping Access Cases ............................................................ 21

4.8.2.2 HOLD Bus Arbitration Implementation ....................................................................... 22

4.8.2.2.1 Processor-Induced Bus Cycles ........................................................................ 22

4.8.2.2.2 External Read ................................................................................................... 22

4.8.2.2.3 External Write ................................................................................................... 22

4.8.2.2.4 HOLD/HLDA External Access TIming .............................................................. 22

4.8.3 External Bus Master Snooping Actions ............................................................................... 25

4.8.3.1 Snoop Miss ................................................................................................................. 25

4.8.3.2 Snoop Hit to a Non-Modified Line .............................................................................. 25

4.8.4 Write-Back Case ................................................................................................................. 25

4.8.5 Write-Back and Pending Access ......................................................................................... 26

4.8.5.1 HOLD/HLDA Write-Back Design Considerations ....................................................... 27

4.8.5.2 AHOLD Bus Arbitration Implementation .................................................................... 28

4.8.5.3 Normal Write-Back ..................................................................................................... 28

4.8.6 Reordering of Write-Backs (AHOLD) with BOFF ................................................................. 29

4.8.7 Special Scenarios For AHOLD Snooping ............................................................................ 30

4.8.7.1 Write Cycle Reordering due to Buffering ................................................................... 30

4.8.7.2 BOFF Write-Back Arbitration Implementation ............................................................ 32

4.8.8 BOFF Design Considerations .............................................................................................. 32

4.8.8.1 Cache Line Fills ......................................................................................................... 32

4.8.8.2 Cache Line Copy-Backs ............................................................................................ 32

4.8.8.3 Locked Accesses ....................................................................................................... 32

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Am5X86 Microprocessor

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