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AM79C981JC

Integrated Multiport Repeater Plus™ (IMR+™)

Advanced Micro Devices 

PRELIMINARY

REQ

Request

Output, Active LOW

This pin is driven LOW when the IMR+ chip is active.

An IMR+ chip is active when it has one or more ports

receiving or colliding or is in the state where it is still

transmitting data from the internal FIFO. The assertion

of this signal signifies that the IMR+ device is request-

ing the use of the DAT and JAM lines for the transfer of

repeated data or collision status to other IMR+ devices.

RST

Reset

Input, Active LOW

Driving this pin LOW resets the internal logic of the

IMR+ device. Reset should be synchronized to the X1

clock if either expansion or port activity monitor is used.

RXD+0–7, RXD–0–7

Receive Data

Input

10BASE-T port differential receive inputs (8 ports).

SCLK

Serial Clock

Input

In normal operating mode, serial data (input or output)

is clocked (in or out) on the rising edge of the signal on

this pin. SCLK is asynchronous to X1 and can operate

up to 10 MHz. In Minimum mode, this pin, together with

the SI pin, controls which information is output on the

SO pin.

SI

Serial In

Input

In normal operating mode, the SI pin is used for test/

management serial input port. Management com-

mands are clocked in on this pin synchronous to the

SCLK input. In Minimum mode, this pin, together with

the SCLK pin, controls which information is output on

the SO pin.

In Minimum mode, the state of SI at the deassertion of

RST signal determines the programming of automatic

polarity detection/correction for 10BASE-T ports.

SO

Serial Out

Output

In normal operating mode, the SO pin is used for test/

management serial output port. Management results

are clocked out on this pin synchronous to the SCLK

input. In Minimum mode, the SO pin is used to serially

output the various status information based on the

state of the SI and SCLK pins.

SCLK

0

0

1

1

SI

SO Output

0

TP Ports Receive Polarity Status + AUI

SQE Test Error Status

1 Bit Rate Error (all ports)

0

TP Ports Link Status + AUI Loopback

Status

1 Port Partitioning Status (all ports)

STR

Store

Input/Output

As an output, this pin goes HIGH for two X1 clock cycle

times after the nine carrier sense bits are output on the

CRS pin. Note that the carrier sense signals arriving

from each port are latched internally, so that an active

transition is remembered between samples. The accu-

racy of the carrier sense signals produced in this man-

ner is 10 bit times (1 µs).

When used in conjunction with the HIMIB device, the

STR pin will be configured as an input automatically

after a hardware reset. The HIMIB device uses this

input to communicate with the IMR+ device. When

used with the HIMIB chip, this pin must be pulled up via

a high-value resistor.

TEST

Test Pin

Input, Active HIGH

This pin should be tied LOW for normal operation. If

this pin is driven HIGH, then the IMR+ device can be

programmed for Loopback Test mode. Also, if this pin is

HIGH when the RST pin is deasserted, the IMR+ de-

vice will enter the Minimum mode. An inverted version

of the RST signal can be used to program the device

into the Minimum mode.

Test

0

0

1

1

SI

Functions

0 Normal Management Mode

1 Normal Management Mode

0

Minimum Mode, Receive Polarity

Correction Disabled

1

Minimum Mode, Receive Polarity

Correction Enabled

Am79C981

1–77

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